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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope %s3 4; Although it's modeled without any control flow in order to get better code5; out of the structurizer, @llvm.amdgcn.kill actually ends the thread that calls6; it with "true". In case it's called in a provably infinite loop, we still7; need to successfully exit and export something, even if we can't know where8; to jump to in the LLVM IR. Therefore we insert a null export ourselves in9; this case right before the s_endpgm to avoid GPU hangs, which is what this10; tests.11 12; FIXME: Immediate value 0x41200000 should be folded into the v_cmp instruction.13define amdgpu_ps void @return_void(float %0) #0 {14; CHECK-LABEL: return_void:15; CHECK: ; %bb.0: ; %main_body16; CHECK-NEXT: s_mov_b64 s[0:1], exec17; CHECK-NEXT: s_mov_b32 s2, 0x4120000018; CHECK-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v019; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc20; CHECK-NEXT: s_xor_b64 s[2:3], exec, s[2:3]21; CHECK-NEXT: s_cbranch_execz .LBB0_322; CHECK-NEXT: .LBB0_1: ; %loop23; CHECK-NEXT: ; =>This Inner Loop Header: Depth=124; CHECK-NEXT: s_andn2_b64 s[0:1], s[0:1], exec25; CHECK-NEXT: s_cbranch_scc0 .LBB0_626; CHECK-NEXT: ; %bb.2: ; %loop27; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=128; CHECK-NEXT: s_mov_b64 exec, 029; CHECK-NEXT: s_mov_b64 vcc, 030; CHECK-NEXT: s_branch .LBB0_131; CHECK-NEXT: .LBB0_3: ; %Flow132; CHECK-NEXT: s_andn2_saveexec_b64 s[0:1], s[2:3]33; CHECK-NEXT: s_cbranch_execz .LBB0_534; CHECK-NEXT: ; %bb.4: ; %end35; CHECK-NEXT: v_mov_b32_e32 v0, 1.036; CHECK-NEXT: v_mov_b32_e32 v1, 037; CHECK-NEXT: exp mrt0 v1, v1, v1, v0 done vm38; CHECK-NEXT: .LBB0_5: ; %UnifiedReturnBlock39; CHECK-NEXT: s_endpgm40; CHECK-NEXT: .LBB0_6:41; CHECK-NEXT: s_mov_b64 exec, 042; CHECK-NEXT: exp null off, off, off, off done vm43; CHECK-NEXT: s_endpgm44main_body:45 %cmp = fcmp olt float %0, 1.000000e+0146 br i1 %cmp, label %end, label %loop47 48loop:49 call void @llvm.amdgcn.kill(i1 false) #350 br label %loop51 52end:53 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 0., float 0., float 0., float 1., i1 true, i1 true) #354 ret void55}56 57define amdgpu_ps void @return_void_compr(float %0) #0 {58; CHECK-LABEL: return_void_compr:59; CHECK: ; %bb.0: ; %main_body60; CHECK-NEXT: s_mov_b64 s[0:1], exec61; CHECK-NEXT: s_mov_b32 s2, 0x4120000062; CHECK-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v063; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc64; CHECK-NEXT: s_xor_b64 s[2:3], exec, s[2:3]65; CHECK-NEXT: s_cbranch_execz .LBB1_366; CHECK-NEXT: .LBB1_1: ; %loop67; CHECK-NEXT: ; =>This Inner Loop Header: Depth=168; CHECK-NEXT: s_andn2_b64 s[0:1], s[0:1], exec69; CHECK-NEXT: s_cbranch_scc0 .LBB1_670; CHECK-NEXT: ; %bb.2: ; %loop71; CHECK-NEXT: ; in Loop: Header=BB1_1 Depth=172; CHECK-NEXT: s_mov_b64 exec, 073; CHECK-NEXT: s_mov_b64 vcc, 074; CHECK-NEXT: s_branch .LBB1_175; CHECK-NEXT: .LBB1_3: ; %Flow176; CHECK-NEXT: s_andn2_saveexec_b64 s[0:1], s[2:3]77; CHECK-NEXT: s_cbranch_execz .LBB1_578; CHECK-NEXT: ; %bb.4: ; %end79; CHECK-NEXT: v_mov_b32_e32 v0, 080; CHECK-NEXT: exp mrt0 v0, off, v0, off done compr vm81; CHECK-NEXT: .LBB1_5: ; %UnifiedReturnBlock82; CHECK-NEXT: s_endpgm83; CHECK-NEXT: .LBB1_6:84; CHECK-NEXT: s_mov_b64 exec, 085; CHECK-NEXT: exp null off, off, off, off done vm86; CHECK-NEXT: s_endpgm87main_body:88 %cmp = fcmp olt float %0, 1.000000e+0189 br i1 %cmp, label %end, label %loop90 91loop:92 call void @llvm.amdgcn.kill(i1 false) #393 br label %loop94 95end:96 call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 5, <2 x i16> < i16 0, i16 0 >, <2 x i16> < i16 0, i16 0 >, i1 true, i1 true) #397 ret void98}99 100; test the case where there's only a kill in an infinite loop101define amdgpu_ps void @only_kill() #0 {102; CHECK-LABEL: only_kill:103; CHECK: ; %bb.0: ; %main_body104; CHECK-NEXT: s_mov_b64 s[0:1], exec105; CHECK-NEXT: .LBB2_1: ; %loop106; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1107; CHECK-NEXT: s_andn2_b64 s[0:1], s[0:1], exec108; CHECK-NEXT: s_cbranch_scc0 .LBB2_4109; CHECK-NEXT: ; %bb.2: ; %loop110; CHECK-NEXT: ; in Loop: Header=BB2_1 Depth=1111; CHECK-NEXT: s_mov_b64 exec, 0112; CHECK-NEXT: s_mov_b64 vcc, exec113; CHECK-NEXT: s_cbranch_execnz .LBB2_1114; CHECK-NEXT: ; %bb.3: ; %DummyReturnBlock115; CHECK-NEXT: s_endpgm116; CHECK-NEXT: .LBB2_4:117; CHECK-NEXT: s_mov_b64 exec, 0118; CHECK-NEXT: exp null off, off, off, off done vm119; CHECK-NEXT: s_endpgm120main_body:121 br label %loop122 123loop:124 call void @llvm.amdgcn.kill(i1 false) #3125 br label %loop126}127 128; Check that the epilog is the final block129define amdgpu_ps float @return_nonvoid(float %0) #0 {130; CHECK-LABEL: return_nonvoid:131; CHECK: ; %bb.0: ; %main_body132; CHECK-NEXT: s_mov_b64 s[0:1], exec133; CHECK-NEXT: s_mov_b32 s2, 0x41200000134; CHECK-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v0135; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc136; CHECK-NEXT: s_xor_b64 s[2:3], exec, s[2:3]137; CHECK-NEXT: s_cbranch_execz .LBB3_3138; CHECK-NEXT: .LBB3_1: ; %loop139; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1140; CHECK-NEXT: s_andn2_b64 s[0:1], s[0:1], exec141; CHECK-NEXT: s_cbranch_scc0 .LBB3_4142; CHECK-NEXT: ; %bb.2: ; %loop143; CHECK-NEXT: ; in Loop: Header=BB3_1 Depth=1144; CHECK-NEXT: s_mov_b64 exec, 0145; CHECK-NEXT: s_mov_b64 vcc, exec146; CHECK-NEXT: s_cbranch_execnz .LBB3_1147; CHECK-NEXT: .LBB3_3: ; %Flow1148; CHECK-NEXT: s_or_b64 exec, exec, s[2:3]149; CHECK-NEXT: v_mov_b32_e32 v0, 0150; CHECK-NEXT: s_branch .LBB3_5151; CHECK-NEXT: .LBB3_4:152; CHECK-NEXT: s_mov_b64 exec, 0153; CHECK-NEXT: exp null off, off, off, off done vm154; CHECK-NEXT: s_endpgm155; CHECK-NEXT: .LBB3_5:156main_body:157 %cmp = fcmp olt float %0, 1.000000e+01158 br i1 %cmp, label %end, label %loop159 160loop:161 call void @llvm.amdgcn.kill(i1 false) #3162 br label %loop163 164end:165 ret float 0.166}167 168declare void @llvm.amdgcn.kill(i1) #0169declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg) #0170declare void @llvm.amdgcn.exp.compr.v2i16(i32 immarg, i32 immarg, <2 x i16>, <2 x i16>, i1 immarg, i1 immarg) #0171 172attributes #0 = { nounwind }173