62 lines · plain
1; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -amdgpu-enable-lower-module-lds=0 -show-mc-encoding < %s | FileCheck -check-prefixes=GCN %s2; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -amdgpu-enable-lower-module-lds=0 -filetype=obj < %s | llvm-readobj -r --syms - | FileCheck -check-prefixes=ELF %s3 4@lds.external = external unnamed_addr addrspace(3) global [0 x i32]5@lds.defined = unnamed_addr addrspace(3) global [8 x i32] poison, align 86 7; ELF: Relocations [8; ELF-NEXT: Section (3) .rel.text {9; ELF-NEXT: 0x{{[0-9A-F]*}} R_AMDGPU_ABS32_LO lds.external10; ELF-NEXT: 0x{{[0-9A-F]*}} R_AMDGPU_ABS32_LO lds.defined11; ELF-NEXT: }12; ELF-NEXT: ]13 14; ELF: Symbol {15; ELF: Name: lds.external16; ELF-NEXT: Value: 0x417; ELF-NEXT: Size: 018; ELF-NEXT: Binding: Global (0x1)19; ELF-NEXT: Type: Object (0x1)20; ELF-NEXT: Other: 021; ELF-NEXT: Section: Processor Specific (0xFF00)22; ELF-NEXT: }23 24; ELF: Symbol {25; ELF: Name: lds.defined26; ELF-NEXT: Value: 0x827; ELF-NEXT: Size: 3228; ELF-NEXT: Binding: Global (0x1)29; ELF-NEXT: Type: Object (0x1)30; ELF-NEXT: Other: 031; ELF-NEXT: Section: Processor Specific (0xFF00)32; ELF-NEXT: }33 34; GCN-LABEL: {{^}}test_basic:35; GCN: s_mov_b32 s0, lds.external@abs32@lo ; encoding: [0xff,0x00,0x80,0xbe,A,A,A,A]36; GCN-NEXT: ; fixup A - offset: 4, value: lds.external@abs32@lo, kind: FK_Data_4{{$}}37;38; GCN: s_lshl2_add_u32 s0, s2, lds.defined@abs32@lo ; encoding: [0x02,0xff,0x80,0x97,A,A,A,A]39; GCN-NEXT: ; fixup A - offset: 4, value: lds.defined@abs32@lo, kind: FK_Data_4{{$}}40;41; GCN: .globl lds.external42; GCN: .amdgpu_lds lds.external, 0, 443; GCN: .globl lds.defined44; GCN: .amdgpu_lds lds.defined, 32, 845define amdgpu_gs float @test_basic(i32 inreg %wave, i32 %arg1) #0 {46main_body:47 %gep0 = getelementptr [0 x i32], ptr addrspace(3) @lds.external, i32 0, i32 %arg148 %tmp = load i32, ptr addrspace(3) %gep049 50 %gep1 = getelementptr [8 x i32], ptr addrspace(3) @lds.defined, i32 0, i32 %wave51 store i32 123, ptr addrspace(3) %gep152 53 %r = bitcast i32 %tmp to float54 ret float %r55}56 57; Function Attrs: convergent nounwind readnone58declare i64 @llvm.amdgcn.icmp.i64.i32(i32, i32, i32) #459 60attributes #0 = { "no-signed-zeros-fp-math"="true" }61attributes #4 = { convergent nounwind readnone }62