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1; RUN: llc -mtriple=amdgcn -mcpu=gfx906 -amdgpu-s-branch-bits=6 -amdgpu-long-branch-factor=0 < %s | FileCheck -check-prefix=GCN %s2 3 4; Restrict maximum branch to between +31 and -32 dwords5declare void @llvm.amdgcn.s.sleep(i32) #06 7@name1 = external addrspace(1) global i328@name2 = external addrspace(1) global i329@name3 = external addrspace(1) global i3210 11; GCN-LABEL: {{^}}branch_offset_test:12; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 013; GCN-NEXT: s_cbranch_scc0 [[BB2:.LBB[0-9]+_[0-9]+]]14; GCN-NEXT: ; %bb.3: ; %bb15; GCN-NEXT: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]16; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}17; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[BB3:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&429496729518; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[BB3]]-[[POST_GETPC]])>>3219; GCN-NEXT: s_setpc_b64 s[[[PC_LO]]:[[PC_HI]]]20; GCN-NEXT: [[BB2]]: ; %bb221; GCN-NEXT: s_getpc_b64 s[[[PC_LO]]:[[PC_HI]]]22 23; GCN: [[BB3]]: ; %bb324define amdgpu_kernel void @branch_offset_test(ptr addrspace(1) %arg, i32 %cnd) #0 {25bb:26 %cmp = icmp eq i32 %cnd, 027 br i1 %cmp, label %bb3, label %bb2 ; +8 dword branch28 29bb2:30 store i32 1, ptr addrspace(1) @name131 store i32 2, ptr addrspace(1) @name232 store i32 3, ptr addrspace(1) @name333 call void @llvm.amdgcn.s.sleep(i32 0)34 br label %bb335 36bb3:37 store volatile i32 %cnd, ptr addrspace(1) %arg38 ret void39}40