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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GCN,GCN-SDAG %s3; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GCN,GCN-GISEL %s4 5define amdgpu_ps i64 @s_add_u64(i64 inreg %a) {6; GCN-LABEL: s_add_u64:7; GCN: ; %bb.0:8; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 19; GCN-NEXT: s_add_nc_u64 s[0:1], s[0:1], 0xf1234567810; GCN-NEXT: ; return to shader part epilog11 %result = add i64 %a, 6472992933612 ret i64 %result13}14 15define amdgpu_ps void @v_add_u64(i64 %a, ptr addrspace(1) %out) {16; GCN-LABEL: v_add_u64:17; GCN: ; %bb.0:18; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 119; GCN-NEXT: v_add_nc_u64_e32 v[0:1], 0xf12345678, v[0:1]20; GCN-NEXT: global_store_b64 v[2:3], v[0:1], off21; GCN-NEXT: s_endpgm22 %result = add i64 %a, 6472992933623 store i64 %result, ptr addrspace(1) %out, align 824 ret void25}26 27define amdgpu_ps i64 @s_add_neg_u64(i64 inreg %a) {28; GCN-LABEL: s_add_neg_u64:29; GCN: ; %bb.0:30; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 131; GCN-NEXT: s_add_nc_u64 s[0:1], s[0:1], 0xfffffff0edcba98832; GCN-NEXT: ; return to shader part epilog33 %result = sub i64 %a, 6472992933634 ret i64 %result35}36 37define amdgpu_ps void @v_add_neg_u64(i64 %a, ptr addrspace(1) %out) {38; GCN-LABEL: v_add_neg_u64:39; GCN: ; %bb.0:40; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 141; GCN-NEXT: v_add_nc_u64_e32 v[0:1], 0xfffffff0edcba988, v[0:1]42; GCN-NEXT: global_store_b64 v[2:3], v[0:1], off43; GCN-NEXT: s_endpgm44 %result = sub i64 %a, 6472992933645 store i64 %result, ptr addrspace(1) %out, align 846 ret void47}48 49define amdgpu_ps i64 @s_sub_u64(i64 inreg %a) {50; GCN-LABEL: s_sub_u64:51; GCN: ; %bb.0:52; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 153; GCN-NEXT: s_sub_nc_u64 s[0:1], 0xf12345678, s[0:1]54; GCN-NEXT: ; return to shader part epilog55 %result = sub i64 64729929336, %a56 ret i64 %result57}58 59define amdgpu_ps void @v_sub_u64(i64 %a, ptr addrspace(1) %out) {60; GCN-LABEL: v_sub_u64:61; GCN: ; %bb.0:62; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 163; GCN-NEXT: v_sub_nc_u64_e32 v[0:1], 0xf12345678, v[0:1]64; GCN-NEXT: global_store_b64 v[2:3], v[0:1], off65; GCN-NEXT: s_endpgm66 %result = sub i64 64729929336, %a67 store i64 %result, ptr addrspace(1) %out, align 868 ret void69}70 71define void @v_mov_b64_double(ptr addrspace(1) %ptr) {72; GCN-LABEL: v_mov_b64_double:73; GCN: ; %bb.0:74; GCN-NEXT: s_wait_loadcnt_dscnt 0x075; GCN-NEXT: s_wait_kmcnt 0x076; GCN-NEXT: v_mov_b64_e32 v[2:3], 0x406323333333333377; GCN-NEXT: global_atomic_add_f64 v[0:1], v[2:3], off scope:SCOPE_SYS78; GCN-NEXT: s_set_pc_i64 s[30:31]79 %result = atomicrmw fadd ptr addrspace(1) %ptr, double 153.1 monotonic80 ret void81}82 83define void @v_mov_b64_int(ptr addrspace(1) %ptr) {84; GCN-LABEL: v_mov_b64_int:85; GCN: ; %bb.0:86; GCN-NEXT: s_wait_loadcnt_dscnt 0x087; GCN-NEXT: s_wait_kmcnt 0x088; GCN-NEXT: v_mov_b64_e32 v[2:3], 0xf1234567889; GCN-NEXT: global_atomic_add_u64 v[0:1], v[2:3], off scope:SCOPE_SYS90; GCN-NEXT: s_set_pc_i64 s[30:31]91 %result = atomicrmw add ptr addrspace(1) %ptr, i64 64729929336 monotonic92 ret void93}94 95define void @store_double(ptr addrspace(1) %ptr) {96; GCN-LABEL: store_double:97; GCN: ; %bb.0:98; GCN-NEXT: s_wait_loadcnt_dscnt 0x099; GCN-NEXT: s_wait_kmcnt 0x0100; GCN-NEXT: v_mov_b64_e32 v[2:3], 0x4063233333333333101; GCN-NEXT: global_store_b64 v[0:1], v[2:3], off102; GCN-NEXT: s_set_pc_i64 s[30:31]103 store double 153.1, ptr addrspace(1) %ptr104 ret void105}106 107define i1 @class_f64() noinline optnone {108; GCN-SDAG-LABEL: class_f64:109; GCN-SDAG: ; %bb.0:110; GCN-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0111; GCN-SDAG-NEXT: s_wait_kmcnt 0x0112; GCN-SDAG-NEXT: s_mov_b32 s2, 1113; GCN-SDAG-NEXT: s_mov_b64 s[0:1], 0x4063233333333333114; GCN-SDAG-NEXT: v_cmp_class_f64_e64 s0, s[0:1], s2115; GCN-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0116; GCN-SDAG-NEXT: s_set_pc_i64 s[30:31]117;118; GCN-GISEL-LABEL: class_f64:119; GCN-GISEL: ; %bb.0:120; GCN-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0121; GCN-GISEL-NEXT: s_wait_kmcnt 0x0122; GCN-GISEL-NEXT: s_mov_b32 s2, 1123; GCN-GISEL-NEXT: s_mov_b64 s[0:1], 0x4063233333333333124; GCN-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]125; GCN-GISEL-NEXT: v_mov_b32_e32 v2, s2126; GCN-GISEL-NEXT: v_cmp_class_f64_e64 s0, v[0:1], v2127; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 1128; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0129; GCN-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, v0, s0130; GCN-GISEL-NEXT: s_set_pc_i64 s[30:31]131 %result = call i1 @llvm.amdgcn.class.f64(double 153.1, i32 1) nounwind readnone132 ret i1 %result133}134 135define double @rsq_f64() {136; GCN-LABEL: rsq_f64:137; GCN: ; %bb.0:138; GCN-NEXT: s_wait_loadcnt_dscnt 0x0139; GCN-NEXT: s_wait_kmcnt 0x0140; GCN-NEXT: v_rsq_f64_e32 v[0:1], 0x4063233333333333141; GCN-NEXT: s_set_pc_i64 s[30:31]142 %result = call double @llvm.amdgcn.rsq.f64(double 153.1) nounwind readnone143 ret double %result144}145 146define amdgpu_ps i64 @s_and_b64(i64 inreg %a) {147; GCN-LABEL: s_and_b64:148; GCN: ; %bb.0:149; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1150; GCN-NEXT: s_and_b64 s[0:1], s[0:1], 0xf12345678151; GCN-NEXT: ; return to shader part epilog152 %result = and i64 %a, 64729929336153 ret i64 %result154}155 156; No V_AND_B64 instruction, it has to be split157 158define amdgpu_ps void @v_and_b64(i64 %a, ptr addrspace(1) %out) {159; GCN-SDAG-LABEL: v_and_b64:160; GCN-SDAG: ; %bb.0:161; GCN-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1162; GCN-SDAG-NEXT: v_and_b32_e32 v1, 15, v1163; GCN-SDAG-NEXT: v_and_b32_e32 v0, 0x12345678, v0164; GCN-SDAG-NEXT: global_store_b64 v[2:3], v[0:1], off165; GCN-SDAG-NEXT: s_endpgm166;167; GCN-GISEL-LABEL: v_and_b64:168; GCN-GISEL: ; %bb.0:169; GCN-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1170; GCN-GISEL-NEXT: v_and_b32_e32 v0, 0x12345678, v0171; GCN-GISEL-NEXT: v_and_b32_e32 v1, 15, v1172; GCN-GISEL-NEXT: global_store_b64 v[2:3], v[0:1], off173; GCN-GISEL-NEXT: s_endpgm174 %result = and i64 %a, 64729929336175 store i64 %result, ptr addrspace(1) %out, align 8176 ret void177}178 179define amdgpu_ps <2 x float> @v_add_f64_200.1(double %a) {180; GCN-LABEL: v_add_f64_200.1:181; GCN: ; %bb.0:182; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1183; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0184; GCN-NEXT: v_add_f64_e32 v[0:1], 0x4069033333333333, v[0:1]185; GCN-NEXT: ; return to shader part epilog186 %add = fadd double %a, 200.1187 %ret = bitcast double %add to <2 x float>188 ret <2 x float> %ret189}190 191; 200.0 can be encoded as 32-bit literal192 193define amdgpu_ps <2 x float> @v_add_f64_200.0(double %a) {194; GCN-LABEL: v_add_f64_200.0:195; GCN: ; %bb.0:196; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1197; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0198; GCN-NEXT: v_add_f64_e32 v[0:1], 0x40690000, v[0:1]199; GCN-NEXT: ; return to shader part epilog200 %add = fadd double %a, 200.0201 %ret = bitcast double %add to <2 x float>202 ret <2 x float> %ret203}204 205; No folding into VOP3206 207define amdgpu_ps <2 x float> @v_lshl_add_u64(i64 %a) {208; GCN-SDAG-LABEL: v_lshl_add_u64:209; GCN-SDAG: ; %bb.0:210; GCN-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1211; GCN-SDAG-NEXT: s_mov_b64 s[0:1], 0xf12345678212; GCN-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)213; GCN-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 1, s[0:1]214; GCN-SDAG-NEXT: ; return to shader part epilog215;216; GCN-GISEL-LABEL: v_lshl_add_u64:217; GCN-GISEL: ; %bb.0:218; GCN-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1219; GCN-GISEL-NEXT: v_mov_b64_e32 v[2:3], 0xf12345678220; GCN-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)221; GCN-GISEL-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 1, v[2:3]222; GCN-GISEL-NEXT: ; return to shader part epilog223 %shl = shl i64 %a, 1224 %add = add i64 %shl, 64729929336225 %ret = bitcast i64 %add to <2 x float>226 ret <2 x float> %ret227}228 229; No folding into VOP2 promoted to VOP3230 231define amdgpu_ps <2 x float> @v_fma_f64(double %a, double %b) {232; GCN-SDAG-LABEL: v_fma_f64:233; GCN-SDAG: ; %bb.0:234; GCN-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1235; GCN-SDAG-NEXT: v_fmaak_f64 v[4:5], v[0:1], v[2:3], 0x4063233333333333236; GCN-SDAG-NEXT: v_mov_b64_e32 v[2:3], 0x4069033333333333237; GCN-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)238; GCN-SDAG-NEXT: v_fmaak_f64 v[0:1], v[0:1], v[4:5], 0x4069033333333333239; GCN-SDAG-NEXT: v_fmac_f64_e32 v[2:3], v[0:1], v[4:5]240; GCN-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)241; GCN-SDAG-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3242; GCN-SDAG-NEXT: ; return to shader part epilog243;244; GCN-GISEL-LABEL: v_fma_f64:245; GCN-GISEL: ; %bb.0:246; GCN-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1247; GCN-GISEL-NEXT: v_mov_b64_e32 v[4:5], 0x4063233333333333248; GCN-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)249; GCN-GISEL-NEXT: v_fmac_f64_e32 v[4:5], v[0:1], v[2:3]250; GCN-GISEL-NEXT: v_mov_b64_e32 v[2:3], 0x4069033333333333251; GCN-GISEL-NEXT: v_fmaak_f64 v[0:1], v[0:1], v[4:5], 0x4069033333333333252; GCN-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)253; GCN-GISEL-NEXT: v_fmac_f64_e32 v[2:3], v[0:1], v[4:5]254; GCN-GISEL-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3255; GCN-GISEL-NEXT: ; return to shader part epilog256 %r1 = call double @llvm.fma.f64(double %a, double %b, double 153.1) nounwind readnone257 %r2 = call double @llvm.fma.f64(double %a, double %r1, double 200.1) nounwind readnone258 %r3 = call double @llvm.fma.f64(double %r2, double %r1, double 200.1) nounwind readnone259 %ret = bitcast double %r3 to <2 x float>260 ret <2 x float> %ret261}262 263define amdgpu_ps <2 x float> @v_add_neg_f64(double %a) {264; GCN-SDAG-LABEL: v_add_neg_f64:265; GCN-SDAG: ; %bb.0:266; GCN-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1267; GCN-SDAG-NEXT: s_mov_b64 s[0:1], 0x4069033333333333268; GCN-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0269; GCN-SDAG-NEXT: v_add_f64_e64 v[0:1], -v[0:1], s[0:1]270; GCN-SDAG-NEXT: ; return to shader part epilog271;272; GCN-GISEL-LABEL: v_add_neg_f64:273; GCN-GISEL: ; %bb.0:274; GCN-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1275; GCN-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]276; GCN-GISEL-NEXT: v_mov_b64_e32 v[2:3], 0x4069033333333333277; GCN-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0278; GCN-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)279; GCN-GISEL-NEXT: v_add_f64_e64 v[0:1], -v[0:1], v[2:3]280; GCN-GISEL-NEXT: ; return to shader part epilog281 %fneg = fsub double -0.0, %a282 %add = fadd double %fneg, 200.1283 %ret = bitcast double %add to <2 x float>284 ret <2 x float> %ret285}286 287define amdgpu_ps <2 x float> @v_cndmask(double %a) {288; GCN-SDAG-LABEL: v_cndmask:289; GCN-SDAG: ; %bb.0:290; GCN-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1291; GCN-SDAG-NEXT: v_cmp_eq_f64_e32 vcc_lo, 0, v[0:1]292; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x40632000293; GCN-SDAG-NEXT: v_cndmask_b32_e64 v0, 0x33333333, 0, vcc_lo294; GCN-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)295; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x40690333, v1, vcc_lo296; GCN-SDAG-NEXT: ; return to shader part epilog297;298; GCN-GISEL-LABEL: v_cndmask:299; GCN-GISEL: ; %bb.0:300; GCN-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1301; GCN-GISEL-NEXT: v_cmp_eq_f64_e32 vcc_lo, 0, v[0:1]302; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x40690333303; GCN-GISEL-NEXT: v_cndmask_b32_e64 v0, 0x33333333, 0, vcc_lo304; GCN-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)305; GCN-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0x40632000, vcc_lo306; GCN-GISEL-NEXT: ; return to shader part epilog307 %cmp = fcmp oeq double %a, 0.0308 %sel = select i1 %cmp, double 153.0, double 200.1309 %ret = bitcast double %sel to <2 x float>310 ret <2 x float> %ret311}312 313declare i1 @llvm.amdgcn.class.f64(double, i32) nounwind readnone314declare double @llvm.amdgcn.rsq.f64(double) nounwind readnone315declare double @llvm.fma.f64(double, double, double) nounwind readnone316