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1# RUN: llc -mtriple=amdgcn -run-pass liveintervals -verify-machineinstrs -filetype=null -debug-only=regalloc %s 2>&1 | FileCheck %s2# RUN: llc -mtriple=amdgcn -passes='print<live-intervals>' -filetype=null -debug-only=regalloc %s 2>&1 | FileCheck %s3# REQUIRES: asserts4# We currently maintain a main liveness range which operates like a superset of5# all subregister liveranges. We may need to create additional SSA values at6# merge point in this main liverange even though none of the subregister7# liveranges needed it.8#9# Should see three distinct value numbers:10# CHECK: %0 [{{.*}}:0)[{{.*}}:1)[{{.*}}:2) 0@{{[0-9]+[Berd]}} 1@{{[0-9]+[Berd]}} 2@{{[0-9]+B-phi}}11--- |12 define amdgpu_kernel void @test0() { ret void }13...14---15name: test016registers:17 - { id: 0, class: sreg_64 }18body: |19 bb.0:20 S_NOP 0, implicit-def undef %0.sub021 S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc22 S_BRANCH %bb.223 24 bb.1:25 S_NOP 0, implicit-def %0.sub126 S_NOP 0, implicit %0.sub127 S_BRANCH %bb.228 29 bb.2:30 S_NOP 0, implicit %0.sub031...32