149 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 22# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -run-pass=register-coalescer -verify-coalescing -o - %s | FileCheck %s3 4# Make sure coalescing doesn't produce "no live segment at def" when5# there is a live out implicit_def with subranges.6 7# %1 will be coalesced into %0. %0 is a cross block implicit_def that8# cannot be deleted. The def of %0 in %bb.2 is a live out subregister9# def of the same register. We need to ensure that the resulting10# subrange for %0.sub0 includes the def in %bb.111 12---13name: liveout_implicit_def_super_reg_redefine_sub0_implicit_def14tracksRegLiveness: true15body: |16 ; CHECK-LABEL: name: liveout_implicit_def_super_reg_redefine_sub0_implicit_def17 ; CHECK: bb.0:18 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)19 ; CHECK-NEXT: {{ $}}20 ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit undef $scc21 ; CHECK-NEXT: {{ $}}22 ; CHECK-NEXT: bb.1:23 ; CHECK-NEXT: successors: %bb.3(0x80000000)24 ; CHECK-NEXT: {{ $}}25 ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 026 ; CHECK-NEXT: S_BRANCH %bb.327 ; CHECK-NEXT: {{ $}}28 ; CHECK-NEXT: bb.2:29 ; CHECK-NEXT: successors: %bb.3(0x80000000)30 ; CHECK-NEXT: {{ $}}31 ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = IMPLICIT_DEF32 ; CHECK-NEXT: {{ $}}33 ; CHECK-NEXT: bb.3:34 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]35 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]].sub036 ; CHECK-NEXT: S_ENDPGM 037 bb.0:38 S_CBRANCH_SCC0 %bb.2, implicit undef $scc39 40 bb.1:41 %0:sgpr_128 = IMPLICIT_DEF42 %1:sgpr_32 = S_MOV_B32 043 S_BRANCH %bb.344 45 bb.2:46 undef %0.sub0:sgpr_128 = IMPLICIT_DEF47 %1:sgpr_32 = COPY %0.sub048 49 bb.3:50 S_NOP 0, implicit %051 S_NOP 0, implicit %152 S_ENDPGM 053 54...55 56 57# Redef of sub0 is a meaningful value.58---59name: liveout_implicit_def_redefine_sub0_undef_other60tracksRegLiveness: true61body: |62 ; CHECK-LABEL: name: liveout_implicit_def_redefine_sub0_undef_other63 ; CHECK: bb.0:64 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)65 ; CHECK-NEXT: {{ $}}66 ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit undef $scc67 ; CHECK-NEXT: {{ $}}68 ; CHECK-NEXT: bb.1:69 ; CHECK-NEXT: successors: %bb.3(0x80000000)70 ; CHECK-NEXT: {{ $}}71 ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 072 ; CHECK-NEXT: S_BRANCH %bb.373 ; CHECK-NEXT: {{ $}}74 ; CHECK-NEXT: bb.2:75 ; CHECK-NEXT: successors: %bb.3(0x80000000)76 ; CHECK-NEXT: {{ $}}77 ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 978 ; CHECK-NEXT: {{ $}}79 ; CHECK-NEXT: bb.3:80 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]81 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]].sub082 ; CHECK-NEXT: S_ENDPGM 083 bb.0:84 S_CBRANCH_SCC0 %bb.2, implicit undef $scc85 86 bb.1:87 %0:sgpr_128 = IMPLICIT_DEF88 %1:sgpr_32 = S_MOV_B32 089 S_BRANCH %bb.390 91 bb.2:92 undef %0.sub0:sgpr_128 = S_MOV_B32 993 %1:sgpr_32 = COPY %0.sub094 95 bb.3:96 S_NOP 0, implicit %097 S_NOP 0, implicit %198 S_ENDPGM 099 100...101 102# The initial def of the register doesn't doesn't cover the redefined103# lanes. This had no error but was useful to compare against the104# failing cases.105---106name: only_redefine_undefined_lanes107tracksRegLiveness: true108body: |109 ; CHECK-LABEL: name: only_redefine_undefined_lanes110 ; CHECK: bb.0:111 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)112 ; CHECK-NEXT: {{ $}}113 ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit undef $scc114 ; CHECK-NEXT: {{ $}}115 ; CHECK-NEXT: bb.1:116 ; CHECK-NEXT: successors: %bb.3(0x80000000)117 ; CHECK-NEXT: {{ $}}118 ; CHECK-NEXT: S_NOP 0, implicit-def undef %0.sub1_sub2_sub3119 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec120 ; CHECK-NEXT: S_BRANCH %bb.3121 ; CHECK-NEXT: {{ $}}122 ; CHECK-NEXT: bb.2:123 ; CHECK-NEXT: successors: %bb.3(0x80000000)124 ; CHECK-NEXT: {{ $}}125 ; CHECK-NEXT: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 9, implicit $exec126 ; CHECK-NEXT: {{ $}}127 ; CHECK-NEXT: bb.3:128 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]129 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0130 ; CHECK-NEXT: S_ENDPGM 0131 bb.0:132 S_CBRANCH_SCC0 %bb.2, implicit undef $scc133 134 bb.1:135 S_NOP 0, implicit-def undef %0.sub1_sub2_sub3:vreg_128136 %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec137 S_BRANCH %bb.3138 139 bb.2:140 undef %0.sub0:vreg_128 = V_MOV_B32_e32 9, implicit $exec141 %1:vgpr_32 = COPY %0.sub0142 143 bb.3:144 S_NOP 0, implicit %0145 S_NOP 0, implicit %1146 S_ENDPGM 0147 148...149