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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250-SDAG %s3; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250-GISEL %s4 5declare i32 @llvm.amdgcn.add.min.i32(i32, i32, i32, i1)6declare i32 @llvm.amdgcn.add.max.i32(i32, i32, i32, i1)7declare i32 @llvm.amdgcn.add.min.u32(i32, i32, i32, i1)8declare i32 @llvm.amdgcn.add.max.u32(i32, i32, i32, i1)9declare <2 x i16> @llvm.amdgcn.pk.add.min.i16(<2 x i16>, <2 x i16>, <2 x i16>, i1)10declare <2 x i16> @llvm.amdgcn.pk.add.max.i16(<2 x i16>, <2 x i16>, <2 x i16>, i1)11declare <2 x i16> @llvm.amdgcn.pk.add.min.u16(<2 x i16>, <2 x i16>, <2 x i16>, i1)12declare <2 x i16> @llvm.amdgcn.pk.add.max.u16(<2 x i16>, <2 x i16>, <2 x i16>, i1)13 14define i32 @test_add_min_i32_vvv(i32 %a, i32 %b, i32 %c) {15; GCN-LABEL: test_add_min_i32_vvv:16; GCN: ; %bb.0:17; GCN-NEXT: s_wait_loadcnt_dscnt 0x018; GCN-NEXT: s_wait_kmcnt 0x019; GCN-NEXT: v_add_min_i32 v0, v0, v1, v220; GCN-NEXT: s_set_pc_i64 s[30:31]21 %ret = tail call i32 @llvm.amdgcn.add.min.i32(i32 %a, i32 %b, i32 %c, i1 0)22 ret i32 %ret23}24 25define i32 @test_add_min_i32_ssi_clamp(i32 inreg %a, i32 inreg %b) {26; GCN-LABEL: test_add_min_i32_ssi_clamp:27; GCN: ; %bb.0:28; GCN-NEXT: s_wait_loadcnt_dscnt 0x029; GCN-NEXT: s_wait_kmcnt 0x030; GCN-NEXT: v_add_min_i32 v0, s0, s1, 1 clamp31; GCN-NEXT: s_set_pc_i64 s[30:31]32 %ret = tail call i32 @llvm.amdgcn.add.min.i32(i32 %a, i32 %b, i32 1, i1 1)33 ret i32 %ret34}35 36define i32 @test_add_min_u32_vvv(i32 %a, i32 %b, i32 %c) {37; GCN-LABEL: test_add_min_u32_vvv:38; GCN: ; %bb.0:39; GCN-NEXT: s_wait_loadcnt_dscnt 0x040; GCN-NEXT: s_wait_kmcnt 0x041; GCN-NEXT: v_add_min_u32 v0, v0, v1, v242; GCN-NEXT: s_set_pc_i64 s[30:31]43 %ret = tail call i32 @llvm.amdgcn.add.min.u32(i32 %a, i32 %b, i32 %c, i1 0)44 ret i32 %ret45}46 47define i32 @test_add_min_u32_ssi_clamp(i32 inreg %a, i32 inreg %b) {48; GCN-LABEL: test_add_min_u32_ssi_clamp:49; GCN: ; %bb.0:50; GCN-NEXT: s_wait_loadcnt_dscnt 0x051; GCN-NEXT: s_wait_kmcnt 0x052; GCN-NEXT: v_add_min_u32 v0, s0, s1, 1 clamp53; GCN-NEXT: s_set_pc_i64 s[30:31]54 %ret = tail call i32 @llvm.amdgcn.add.min.u32(i32 %a, i32 %b, i32 1, i1 1)55 ret i32 %ret56}57 58define i32 @test_add_max_i32_vvv(i32 %a, i32 %b, i32 %c) {59; GCN-LABEL: test_add_max_i32_vvv:60; GCN: ; %bb.0:61; GCN-NEXT: s_wait_loadcnt_dscnt 0x062; GCN-NEXT: s_wait_kmcnt 0x063; GCN-NEXT: v_add_max_i32 v0, v0, v1, v264; GCN-NEXT: s_set_pc_i64 s[30:31]65 %ret = tail call i32 @llvm.amdgcn.add.max.i32(i32 %a, i32 %b, i32 %c, i1 0)66 ret i32 %ret67}68 69define i32 @test_add_max_i32_ssi_clamp(i32 inreg %a, i32 inreg %b) {70; GCN-LABEL: test_add_max_i32_ssi_clamp:71; GCN: ; %bb.0:72; GCN-NEXT: s_wait_loadcnt_dscnt 0x073; GCN-NEXT: s_wait_kmcnt 0x074; GCN-NEXT: v_add_max_i32 v0, s0, s1, 1 clamp75; GCN-NEXT: s_set_pc_i64 s[30:31]76 %ret = tail call i32 @llvm.amdgcn.add.max.i32(i32 %a, i32 %b, i32 1, i1 1)77 ret i32 %ret78}79 80define i32 @test_add_max_u32_vvv(i32 %a, i32 %b, i32 %c) {81; GCN-LABEL: test_add_max_u32_vvv:82; GCN: ; %bb.0:83; GCN-NEXT: s_wait_loadcnt_dscnt 0x084; GCN-NEXT: s_wait_kmcnt 0x085; GCN-NEXT: v_add_max_u32 v0, v0, v1, v286; GCN-NEXT: s_set_pc_i64 s[30:31]87 %ret = tail call i32 @llvm.amdgcn.add.max.u32(i32 %a, i32 %b, i32 %c, i1 0)88 ret i32 %ret89}90 91define i32 @test_add_max_u32_ssi_clamp(i32 inreg %a, i32 inreg %b) {92; GCN-LABEL: test_add_max_u32_ssi_clamp:93; GCN: ; %bb.0:94; GCN-NEXT: s_wait_loadcnt_dscnt 0x095; GCN-NEXT: s_wait_kmcnt 0x096; GCN-NEXT: v_add_max_u32 v0, s0, s1, 1 clamp97; GCN-NEXT: s_set_pc_i64 s[30:31]98 %ret = tail call i32 @llvm.amdgcn.add.max.u32(i32 %a, i32 %b, i32 1, i1 1)99 ret i32 %ret100}101 102define <2 x i16> @test_add_min_i16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {103; GCN-LABEL: test_add_min_i16_vvv:104; GCN: ; %bb.0:105; GCN-NEXT: s_wait_loadcnt_dscnt 0x0106; GCN-NEXT: s_wait_kmcnt 0x0107; GCN-NEXT: v_pk_add_min_i16 v0, v0, v1, v2108; GCN-NEXT: s_set_pc_i64 s[30:31]109 %ret = tail call <2 x i16> @llvm.amdgcn.pk.add.min.i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, i1 0)110 ret <2 x i16> %ret111}112 113define <2 x i16> @test_add_min_i16_ssi_clamp(<2 x i16> inreg %a, <2 x i16> inreg %b) {114; GCN-LABEL: test_add_min_i16_ssi_clamp:115; GCN: ; %bb.0:116; GCN-NEXT: s_wait_loadcnt_dscnt 0x0117; GCN-NEXT: s_wait_kmcnt 0x0118; GCN-NEXT: v_pk_add_min_i16 v0, s0, s1, 1 op_sel_hi:[1,1,0] clamp119; GCN-NEXT: s_set_pc_i64 s[30:31]120 %ret = tail call <2 x i16> @llvm.amdgcn.pk.add.min.i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> <i16 1, i16 1>, i1 1)121 ret <2 x i16> %ret122}123 124define <2 x i16> @test_add_min_u16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {125; GCN-LABEL: test_add_min_u16_vvv:126; GCN: ; %bb.0:127; GCN-NEXT: s_wait_loadcnt_dscnt 0x0128; GCN-NEXT: s_wait_kmcnt 0x0129; GCN-NEXT: v_pk_add_min_u16 v0, v0, v1, v2130; GCN-NEXT: s_set_pc_i64 s[30:31]131 %ret = tail call <2 x i16> @llvm.amdgcn.pk.add.min.u16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, i1 0)132 ret <2 x i16> %ret133}134 135define <2 x i16> @test_add_min_u16_ssi_clamp(<2 x i16> inreg %a, <2 x i16> inreg %b) {136; GCN-LABEL: test_add_min_u16_ssi_clamp:137; GCN: ; %bb.0:138; GCN-NEXT: s_wait_loadcnt_dscnt 0x0139; GCN-NEXT: s_wait_kmcnt 0x0140; GCN-NEXT: v_pk_add_min_u16 v0, s0, s1, 1 op_sel_hi:[1,1,0] clamp141; GCN-NEXT: s_set_pc_i64 s[30:31]142 %ret = tail call <2 x i16> @llvm.amdgcn.pk.add.min.u16(<2 x i16> %a, <2 x i16> %b, <2 x i16> <i16 1, i16 1>, i1 1)143 ret <2 x i16> %ret144}145 146define <2 x i16> @test_add_max_i16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {147; GCN-LABEL: test_add_max_i16_vvv:148; GCN: ; %bb.0:149; GCN-NEXT: s_wait_loadcnt_dscnt 0x0150; GCN-NEXT: s_wait_kmcnt 0x0151; GCN-NEXT: v_pk_add_max_i16 v0, v0, v1, v2152; GCN-NEXT: s_set_pc_i64 s[30:31]153 %ret = tail call <2 x i16> @llvm.amdgcn.pk.add.max.i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, i1 0)154 ret <2 x i16> %ret155}156 157define <2 x i16> @test_add_max_i16_ssi_clamp(<2 x i16> inreg %a, <2 x i16> inreg %b) {158; GCN-LABEL: test_add_max_i16_ssi_clamp:159; GCN: ; %bb.0:160; GCN-NEXT: s_wait_loadcnt_dscnt 0x0161; GCN-NEXT: s_wait_kmcnt 0x0162; GCN-NEXT: v_pk_add_max_i16 v0, s0, s1, 1 op_sel_hi:[1,1,0] clamp163; GCN-NEXT: s_set_pc_i64 s[30:31]164 %ret = tail call <2 x i16> @llvm.amdgcn.pk.add.max.i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> <i16 1, i16 1>, i1 1)165 ret <2 x i16> %ret166}167 168define <2 x i16> @test_add_max_u16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {169; GCN-LABEL: test_add_max_u16_vvv:170; GCN: ; %bb.0:171; GCN-NEXT: s_wait_loadcnt_dscnt 0x0172; GCN-NEXT: s_wait_kmcnt 0x0173; GCN-NEXT: v_pk_add_max_u16 v0, v0, v1, v2174; GCN-NEXT: s_set_pc_i64 s[30:31]175 %ret = tail call <2 x i16> @llvm.amdgcn.pk.add.max.u16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, i1 0)176 ret <2 x i16> %ret177}178 179define <2 x i16> @test_add_max_u16_ssi_clamp(<2 x i16> inreg %a, <2 x i16> inreg %b) {180; GCN-LABEL: test_add_max_u16_ssi_clamp:181; GCN: ; %bb.0:182; GCN-NEXT: s_wait_loadcnt_dscnt 0x0183; GCN-NEXT: s_wait_kmcnt 0x0184; GCN-NEXT: v_pk_add_max_u16 v0, s0, s1, 1 op_sel_hi:[1,1,0] clamp185; GCN-NEXT: s_set_pc_i64 s[30:31]186 %ret = tail call <2 x i16> @llvm.amdgcn.pk.add.max.u16(<2 x i16> %a, <2 x i16> %b, <2 x i16> <i16 1, i16 1>, i1 1)187 ret <2 x i16> %ret188}189;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:190; GFX1250-GISEL: {{.*}}191; GFX1250-SDAG: {{.*}}192