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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32 < %s | FileCheck -check-prefixes=CHECK,GFX10 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize32 < %s | FileCheck -check-prefixes=CHECK,GFX11 %s4 5declare i32 @llvm.amdgcn.ballot.i32(i1)6declare i32 @llvm.ctpop.i32(i32)7 8; Test ballot(0)9 10define amdgpu_cs i32 @constant_false() {11; CHECK-LABEL: constant_false:12; CHECK: ; %bb.0:13; CHECK-NEXT: s_mov_b32 s0, 014; CHECK-NEXT: ; return to shader part epilog15 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 0)16 ret i32 %ballot17}18 19; Test ballot(1)20 21define amdgpu_cs i32 @constant_true() {22; CHECK-LABEL: constant_true:23; CHECK: ; %bb.0:24; CHECK-NEXT: s_mov_b32 s0, exec_lo25; CHECK-NEXT: ; return to shader part epilog26 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 1)27 ret i32 %ballot28}29 30; Test ballot of a non-comparison operation31 32define amdgpu_cs i32 @non_compare(i32 %x) {33; CHECK-LABEL: non_compare:34; CHECK: ; %bb.0:35; CHECK-NEXT: v_and_b32_e32 v0, 1, v036; CHECK-NEXT: v_cmp_ne_u32_e64 s0, 0, v037; CHECK-NEXT: ; return to shader part epilog38 %trunc = trunc i32 %x to i139 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %trunc)40 ret i32 %ballot41}42 43; Test ballot of comparisons44 45define amdgpu_cs i32 @compare_ints(i32 %x, i32 %y) {46; CHECK-LABEL: compare_ints:47; CHECK: ; %bb.0:48; CHECK-NEXT: v_cmp_eq_u32_e64 s0, v0, v149; CHECK-NEXT: ; return to shader part epilog50 %cmp = icmp eq i32 %x, %y51 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %cmp)52 ret i32 %ballot53}54 55define amdgpu_cs i32 @compare_int_with_constant(i32 %x) {56; CHECK-LABEL: compare_int_with_constant:57; CHECK: ; %bb.0:58; CHECK-NEXT: v_cmp_lt_i32_e64 s0, 0x62, v059; CHECK-NEXT: ; return to shader part epilog60 %cmp = icmp sge i32 %x, 9961 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %cmp)62 ret i32 %ballot63}64 65define amdgpu_cs i32 @compare_floats(float %x, float %y) {66; CHECK-LABEL: compare_floats:67; CHECK: ; %bb.0:68; CHECK-NEXT: v_cmp_gt_f32_e64 s0, v0, v169; CHECK-NEXT: ; return to shader part epilog70 %cmp = fcmp ogt float %x, %y71 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %cmp)72 ret i32 %ballot73}74 75define amdgpu_cs i32 @ctpop_of_ballot(float %x, float %y) {76; CHECK-LABEL: ctpop_of_ballot:77; CHECK: ; %bb.0:78; CHECK-NEXT: v_cmp_gt_f32_e32 vcc_lo, v0, v179; CHECK-NEXT: s_bcnt1_i32_b32 s0, vcc_lo80; CHECK-NEXT: ; return to shader part epilog81 %cmp = fcmp ogt float %x, %y82 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %cmp)83 %bcnt = call i32 @llvm.ctpop.i32(i32 %ballot)84 ret i32 %bcnt85}86 87define amdgpu_cs i32 @branch_divergent_ballot_ne_zero_non_compare(i32 %v) {88; CHECK-LABEL: branch_divergent_ballot_ne_zero_non_compare:89; CHECK: ; %bb.0:90; CHECK-NEXT: v_and_b32_e32 v0, 1, v091; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v092; CHECK-NEXT: s_cbranch_vccz .LBB7_293; CHECK-NEXT: ; %bb.1: ; %true94; CHECK-NEXT: s_mov_b32 s0, 4295; CHECK-NEXT: s_branch .LBB7_396; CHECK-NEXT: .LBB7_2: ; %false97; CHECK-NEXT: s_mov_b32 s0, 3398; CHECK-NEXT: s_branch .LBB7_399; CHECK-NEXT: .LBB7_3:100 %c = trunc i32 %v to i1101 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)102 %ballot_ne_zero = icmp ne i32 %ballot, 0103 br i1 %ballot_ne_zero, label %true, label %false104true:105 ret i32 42106false:107 ret i32 33108}109 110define amdgpu_cs i32 @branch_uniform_ballot_ne_zero_non_compare(i32 inreg %v) {111; CHECK-LABEL: branch_uniform_ballot_ne_zero_non_compare:112; CHECK: ; %bb.0:113; CHECK-NEXT: s_bitcmp0_b32 s0, 0114; CHECK-NEXT: s_cbranch_scc1 .LBB8_2115; CHECK-NEXT: ; %bb.1: ; %true116; CHECK-NEXT: s_mov_b32 s0, 42117; CHECK-NEXT: s_branch .LBB8_3118; CHECK-NEXT: .LBB8_2: ; %false119; CHECK-NEXT: s_mov_b32 s0, 33120; CHECK-NEXT: s_branch .LBB8_3121; CHECK-NEXT: .LBB8_3:122 %c = trunc i32 %v to i1123 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)124 %ballot_ne_zero = icmp ne i32 %ballot, 0125 br i1 %ballot_ne_zero, label %true, label %false126true:127 ret i32 42128false:129 ret i32 33130}131 132define amdgpu_cs i32 @branch_divergent_ballot_eq_zero_non_compare(i32 %v) {133; CHECK-LABEL: branch_divergent_ballot_eq_zero_non_compare:134; CHECK: ; %bb.0:135; CHECK-NEXT: v_and_b32_e32 v0, 1, v0136; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0137; CHECK-NEXT: s_cbranch_vccz .LBB9_2138; CHECK-NEXT: ; %bb.1: ; %false139; CHECK-NEXT: s_mov_b32 s0, 33140; CHECK-NEXT: s_branch .LBB9_3141; CHECK-NEXT: .LBB9_2: ; %true142; CHECK-NEXT: s_mov_b32 s0, 42143; CHECK-NEXT: s_branch .LBB9_3144; CHECK-NEXT: .LBB9_3:145 %c = trunc i32 %v to i1146 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)147 %ballot_eq_zero = icmp eq i32 %ballot, 0148 br i1 %ballot_eq_zero, label %true, label %false149true:150 ret i32 42151false:152 ret i32 33153}154 155define amdgpu_cs i32 @branch_uniform_ballot_eq_zero_non_compare(i32 inreg %v) {156; CHECK-LABEL: branch_uniform_ballot_eq_zero_non_compare:157; CHECK: ; %bb.0:158; CHECK-NEXT: s_bitcmp1_b32 s0, 0159; CHECK-NEXT: s_cselect_b32 s0, -1, 0160; CHECK-NEXT: s_and_b32 vcc_lo, exec_lo, s0161; CHECK-NEXT: s_cbranch_vccnz .LBB10_2162; CHECK-NEXT: ; %bb.1: ; %true163; CHECK-NEXT: s_mov_b32 s0, 42164; CHECK-NEXT: s_branch .LBB10_3165; CHECK-NEXT: .LBB10_2: ; %false166; CHECK-NEXT: s_mov_b32 s0, 33167; CHECK-NEXT: s_branch .LBB10_3168; CHECK-NEXT: .LBB10_3:169 %c = trunc i32 %v to i1170 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)171 %ballot_eq_zero = icmp eq i32 %ballot, 0172 br i1 %ballot_eq_zero, label %true, label %false173true:174 ret i32 42175false:176 ret i32 33177}178 179define amdgpu_cs i32 @branch_divergent_ballot_ne_zero_compare(i32 %v) {180; CHECK-LABEL: branch_divergent_ballot_ne_zero_compare:181; CHECK: ; %bb.0:182; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 12, v0183; CHECK-NEXT: s_cbranch_vccz .LBB11_2184; CHECK-NEXT: ; %bb.1: ; %true185; CHECK-NEXT: s_mov_b32 s0, 42186; CHECK-NEXT: s_branch .LBB11_3187; CHECK-NEXT: .LBB11_2: ; %false188; CHECK-NEXT: s_mov_b32 s0, 33189; CHECK-NEXT: s_branch .LBB11_3190; CHECK-NEXT: .LBB11_3:191 %c = icmp ult i32 %v, 12192 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)193 %ballot_ne_zero = icmp ne i32 %ballot, 0194 br i1 %ballot_ne_zero, label %true, label %false195true:196 ret i32 42197false:198 ret i32 33199}200 201define amdgpu_cs i32 @branch_uniform_ballot_ne_zero_compare(i32 inreg %v) {202; CHECK-LABEL: branch_uniform_ballot_ne_zero_compare:203; CHECK: ; %bb.0:204; CHECK-NEXT: s_cmp_gt_u32 s0, 11205; CHECK-NEXT: s_cbranch_scc1 .LBB12_2206; CHECK-NEXT: ; %bb.1: ; %true207; CHECK-NEXT: s_mov_b32 s0, 42208; CHECK-NEXT: s_branch .LBB12_3209; CHECK-NEXT: .LBB12_2: ; %false210; CHECK-NEXT: s_mov_b32 s0, 33211; CHECK-NEXT: s_branch .LBB12_3212; CHECK-NEXT: .LBB12_3:213 %c = icmp ult i32 %v, 12214 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)215 %ballot_ne_zero = icmp ne i32 %ballot, 0216 br i1 %ballot_ne_zero, label %true, label %false217true:218 ret i32 42219false:220 ret i32 33221}222 223define amdgpu_cs i32 @branch_divergent_ballot_eq_zero_compare(i32 %v) {224; CHECK-LABEL: branch_divergent_ballot_eq_zero_compare:225; CHECK: ; %bb.0:226; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 12, v0227; CHECK-NEXT: s_cbranch_vccz .LBB13_2228; CHECK-NEXT: ; %bb.1: ; %false229; CHECK-NEXT: s_mov_b32 s0, 33230; CHECK-NEXT: s_branch .LBB13_3231; CHECK-NEXT: .LBB13_2: ; %true232; CHECK-NEXT: s_mov_b32 s0, 42233; CHECK-NEXT: s_branch .LBB13_3234; CHECK-NEXT: .LBB13_3:235 %c = icmp ult i32 %v, 12236 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)237 %ballot_eq_zero = icmp eq i32 %ballot, 0238 br i1 %ballot_eq_zero, label %true, label %false239true:240 ret i32 42241false:242 ret i32 33243}244 245define amdgpu_cs i32 @branch_uniform_ballot_eq_zero_compare(i32 inreg %v) {246; CHECK-LABEL: branch_uniform_ballot_eq_zero_compare:247; CHECK: ; %bb.0:248; CHECK-NEXT: s_cmp_lt_u32 s0, 12249; CHECK-NEXT: s_cbranch_scc1 .LBB14_2250; CHECK-NEXT: ; %bb.1: ; %true251; CHECK-NEXT: s_mov_b32 s0, 42252; CHECK-NEXT: s_branch .LBB14_3253; CHECK-NEXT: .LBB14_2: ; %false254; CHECK-NEXT: s_mov_b32 s0, 33255; CHECK-NEXT: s_branch .LBB14_3256; CHECK-NEXT: .LBB14_3:257 %c = icmp ult i32 %v, 12258 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)259 %ballot_eq_zero = icmp eq i32 %ballot, 0260 br i1 %ballot_eq_zero, label %true, label %false261true:262 ret i32 42263false:264 ret i32 33265}266 267define amdgpu_cs i32 @branch_divergent_ballot_ne_zero_and(i32 %v1, i32 %v2) {268; CHECK-LABEL: branch_divergent_ballot_ne_zero_and:269; CHECK: ; %bb.0:270; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 12, v0271; CHECK-NEXT: v_cmp_lt_u32_e64 s0, 34, v1272; CHECK-NEXT: s_and_b32 vcc_lo, vcc_lo, s0273; CHECK-NEXT: s_cbranch_vccz .LBB15_2274; CHECK-NEXT: ; %bb.1: ; %true275; CHECK-NEXT: s_mov_b32 s0, 42276; CHECK-NEXT: s_branch .LBB15_3277; CHECK-NEXT: .LBB15_2: ; %false278; CHECK-NEXT: s_mov_b32 s0, 33279; CHECK-NEXT: s_branch .LBB15_3280; CHECK-NEXT: .LBB15_3:281 %v1c = icmp ult i32 %v1, 12282 %v2c = icmp ugt i32 %v2, 34283 %c = and i1 %v1c, %v2c284 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)285 %ballot_ne_zero = icmp ne i32 %ballot, 0286 br i1 %ballot_ne_zero, label %true, label %false287true:288 ret i32 42289false:290 ret i32 33291}292 293define amdgpu_cs i32 @branch_uniform_ballot_ne_zero_and(i32 inreg %v1, i32 inreg %v2) {294; CHECK-LABEL: branch_uniform_ballot_ne_zero_and:295; CHECK: ; %bb.0:296; CHECK-NEXT: s_cmp_gt_u32 s0, 11297; CHECK-NEXT: s_cselect_b32 s0, -1, 0298; CHECK-NEXT: s_cmp_lt_u32 s1, 35299; CHECK-NEXT: s_cselect_b32 s1, -1, 0300; CHECK-NEXT: s_or_b32 s0, s0, s1301; CHECK-NEXT: s_and_b32 vcc_lo, exec_lo, s0302; CHECK-NEXT: s_cbranch_vccnz .LBB16_2303; CHECK-NEXT: ; %bb.1: ; %true304; CHECK-NEXT: s_mov_b32 s0, 42305; CHECK-NEXT: s_branch .LBB16_3306; CHECK-NEXT: .LBB16_2: ; %false307; CHECK-NEXT: s_mov_b32 s0, 33308; CHECK-NEXT: s_branch .LBB16_3309; CHECK-NEXT: .LBB16_3:310 %v1c = icmp ult i32 %v1, 12311 %v2c = icmp ugt i32 %v2, 34312 %c = and i1 %v1c, %v2c313 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)314 %ballot_ne_zero = icmp ne i32 %ballot, 0315 br i1 %ballot_ne_zero, label %true, label %false316true:317 ret i32 42318false:319 ret i32 33320}321 322define amdgpu_cs i32 @branch_divergent_ballot_eq_zero_and(i32 %v1, i32 %v2) {323; CHECK-LABEL: branch_divergent_ballot_eq_zero_and:324; CHECK: ; %bb.0:325; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 12, v0326; CHECK-NEXT: v_cmp_lt_u32_e64 s0, 34, v1327; CHECK-NEXT: s_and_b32 vcc_lo, vcc_lo, s0328; CHECK-NEXT: s_cbranch_vccz .LBB17_2329; CHECK-NEXT: ; %bb.1: ; %false330; CHECK-NEXT: s_mov_b32 s0, 33331; CHECK-NEXT: s_branch .LBB17_3332; CHECK-NEXT: .LBB17_2: ; %true333; CHECK-NEXT: s_mov_b32 s0, 42334; CHECK-NEXT: s_branch .LBB17_3335; CHECK-NEXT: .LBB17_3:336 %v1c = icmp ult i32 %v1, 12337 %v2c = icmp ugt i32 %v2, 34338 %c = and i1 %v1c, %v2c339 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)340 %ballot_eq_zero = icmp eq i32 %ballot, 0341 br i1 %ballot_eq_zero, label %true, label %false342true:343 ret i32 42344false:345 ret i32 33346}347 348define amdgpu_cs i32 @branch_uniform_ballot_eq_zero_and(i32 inreg %v1, i32 inreg %v2) {349; CHECK-LABEL: branch_uniform_ballot_eq_zero_and:350; CHECK: ; %bb.0:351; CHECK-NEXT: s_cmp_lt_u32 s0, 12352; CHECK-NEXT: s_cselect_b32 s0, -1, 0353; CHECK-NEXT: s_cmp_gt_u32 s1, 34354; CHECK-NEXT: s_cselect_b32 s1, -1, 0355; CHECK-NEXT: s_and_b32 s0, s0, s1356; CHECK-NEXT: s_and_b32 vcc_lo, exec_lo, s0357; CHECK-NEXT: s_cbranch_vccnz .LBB18_2358; CHECK-NEXT: ; %bb.1: ; %true359; CHECK-NEXT: s_mov_b32 s0, 42360; CHECK-NEXT: s_branch .LBB18_3361; CHECK-NEXT: .LBB18_2: ; %false362; CHECK-NEXT: s_mov_b32 s0, 33363; CHECK-NEXT: s_branch .LBB18_3364; CHECK-NEXT: .LBB18_3:365 %v1c = icmp ult i32 %v1, 12366 %v2c = icmp ugt i32 %v2, 34367 %c = and i1 %v1c, %v2c368 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)369 %ballot_eq_zero = icmp eq i32 %ballot, 0370 br i1 %ballot_eq_zero, label %true, label %false371true:372 ret i32 42373false:374 ret i32 33375}376 377define amdgpu_cs i32 @branch_uniform_ballot_sgt_N_compare(i32 inreg %v) {378; CHECK-LABEL: branch_uniform_ballot_sgt_N_compare:379; CHECK: ; %bb.0:380; CHECK-NEXT: v_cmp_lt_u32_e64 s0, s0, 12381; CHECK-NEXT: s_cmp_lt_i32 s0, 23382; CHECK-NEXT: s_cbranch_scc1 .LBB19_2383; CHECK-NEXT: ; %bb.1: ; %true384; CHECK-NEXT: s_mov_b32 s0, 42385; CHECK-NEXT: s_branch .LBB19_3386; CHECK-NEXT: .LBB19_2: ; %false387; CHECK-NEXT: s_mov_b32 s0, 33388; CHECK-NEXT: s_branch .LBB19_3389; CHECK-NEXT: .LBB19_3:390 %c = icmp ult i32 %v, 12391 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)392 %bc = icmp sgt i32 %ballot, 22393 br i1 %bc, label %true, label %false394true:395 ret i32 42396false:397 ret i32 33398}399 400declare i32 @llvm.amdgcn.icmp.i32(i1, i1, i32)401 402define amdgpu_cs i32 @branch_divergent_simulated_negated_ballot_ne_zero_and(i32 %v1, i32 %v2) {403; CHECK-LABEL: branch_divergent_simulated_negated_ballot_ne_zero_and:404; CHECK: ; %bb.0:405; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 12, v0406; CHECK-NEXT: v_cmp_lt_u32_e64 s0, 34, v1407; CHECK-NEXT: s_and_b32 vcc_lo, vcc_lo, s0408; CHECK-NEXT: s_cbranch_vccnz .LBB20_2409; CHECK-NEXT: ; %bb.1: ; %true410; CHECK-NEXT: s_mov_b32 s0, 42411; CHECK-NEXT: s_branch .LBB20_3412; CHECK-NEXT: .LBB20_2: ; %false413; CHECK-NEXT: s_mov_b32 s0, 33414; CHECK-NEXT: s_branch .LBB20_3415; CHECK-NEXT: .LBB20_3:416 %v1c = icmp ult i32 %v1, 12417 %v2c = icmp ugt i32 %v2, 34418 %c = and i1 %v1c, %v2c419 %ballot = call i32 @llvm.amdgcn.icmp.i32(i1 %c, i1 0, i32 32) ; ICMP_EQ == 32420 %ballot_ne_zero = icmp ne i32 %ballot, 0421 br i1 %ballot_ne_zero, label %true, label %false422true:423 ret i32 42424false:425 ret i32 33426}427 428define amdgpu_cs i32 @branch_uniform_simulated_negated_ballot_ne_zero_and(i32 inreg %v1, i32 inreg %v2) {429; TODO:430; s_cmp_lt_u32 s0, 12431; s_cselect_b32 s0, -1, 0432; s_cmp_gt_u32 s1, 34433; s_cselect_b32 s1, -1, 0434; s_and_b32 s0, s0, s1435; s_and_b32 s0, s0, exec_lo436; could be improved to:437; s_cmp_lt_u32 s0, 12438; s_cselect_b32 s0, -1, 0439; s_cmp_gt_u32 s1, 34440; s_cselect_b32 s0, s0, 0441; s_and_b32 s0, s0, exec_lo442; By selecting into vcc(_lo) instead, we could even avoid the AND-with-exec.443; CHECK-LABEL: branch_uniform_simulated_negated_ballot_ne_zero_and:444; CHECK: ; %bb.0:445; CHECK-NEXT: s_cmp_lt_u32 s0, 12446; CHECK-NEXT: s_cselect_b32 s0, -1, 0447; CHECK-NEXT: s_cmp_gt_u32 s1, 34448; CHECK-NEXT: s_cselect_b32 s1, -1, 0449; CHECK-NEXT: s_and_b32 s0, s0, s1450; CHECK-NEXT: s_and_b32 s0, s0, exec_lo451; CHECK-NEXT: s_cbranch_scc1 .LBB21_2452; CHECK-NEXT: ; %bb.1: ; %true453; CHECK-NEXT: s_mov_b32 s0, 42454; CHECK-NEXT: s_branch .LBB21_3455; CHECK-NEXT: .LBB21_2: ; %false456; CHECK-NEXT: s_mov_b32 s0, 33457; CHECK-NEXT: s_branch .LBB21_3458; CHECK-NEXT: .LBB21_3:459 %v1c = icmp ult i32 %v1, 12460 %v2c = icmp ugt i32 %v2, 34461 %c = and i1 %v1c, %v2c462 %ballot = call i32 @llvm.amdgcn.icmp.i32(i1 %c, i1 0, i32 32) ; ICMP_EQ == 32463 %ballot_ne_zero = icmp ne i32 %ballot, 0464 br i1 %ballot_ne_zero, label %true, label %false465true:466 ret i32 42467false:468 ret i32 33469}470 471define amdgpu_cs i32 @branch_divergent_simulated_negated_ballot_eq_zero_and(i32 %v1, i32 %v2) {472; CHECK-LABEL: branch_divergent_simulated_negated_ballot_eq_zero_and:473; CHECK: ; %bb.0:474; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 12, v0475; CHECK-NEXT: v_cmp_lt_u32_e64 s0, 34, v1476; CHECK-NEXT: s_and_b32 vcc_lo, vcc_lo, s0477; CHECK-NEXT: s_cbranch_vccnz .LBB22_2478; CHECK-NEXT: ; %bb.1: ; %false479; CHECK-NEXT: s_mov_b32 s0, 33480; CHECK-NEXT: s_branch .LBB22_3481; CHECK-NEXT: .LBB22_2: ; %true482; CHECK-NEXT: s_mov_b32 s0, 42483; CHECK-NEXT: s_branch .LBB22_3484; CHECK-NEXT: .LBB22_3:485 %v1c = icmp ult i32 %v1, 12486 %v2c = icmp ugt i32 %v2, 34487 %c = and i1 %v1c, %v2c488 %ballot = call i32 @llvm.amdgcn.icmp.i32(i1 %c, i1 0, i32 32) ; ICMP_EQ == 32489 %ballot_eq_zero = icmp eq i32 %ballot, 0490 br i1 %ballot_eq_zero, label %true, label %false491true:492 ret i32 42493false:494 ret i32 33495}496 497define amdgpu_cs i32 @branch_uniform_simulated_negated_ballot_eq_zero_and(i32 inreg %v1, i32 inreg %v2) {498; CHECK-LABEL: branch_uniform_simulated_negated_ballot_eq_zero_and:499; CHECK: ; %bb.0:500; CHECK-NEXT: s_cmp_lt_u32 s0, 12501; CHECK-NEXT: s_cselect_b32 s0, -1, 0502; CHECK-NEXT: s_cmp_gt_u32 s1, 34503; CHECK-NEXT: s_cselect_b32 s1, -1, 0504; CHECK-NEXT: s_and_b32 s0, s0, s1505; CHECK-NEXT: s_and_b32 s0, s0, exec_lo506; CHECK-NEXT: s_cbranch_scc1 .LBB23_2507; CHECK-NEXT: ; %bb.1: ; %false508; CHECK-NEXT: s_mov_b32 s0, 33509; CHECK-NEXT: s_branch .LBB23_3510; CHECK-NEXT: .LBB23_2: ; %true511; CHECK-NEXT: s_mov_b32 s0, 42512; CHECK-NEXT: s_branch .LBB23_3513; CHECK-NEXT: .LBB23_3:514 %v1c = icmp ult i32 %v1, 12515 %v2c = icmp ugt i32 %v2, 34516 %c = and i1 %v1c, %v2c517 %ballot = call i32 @llvm.amdgcn.icmp.i32(i1 %c, i1 0, i32 32) ; ICMP_EQ == 32518 %ballot_eq_zero = icmp eq i32 %ballot, 0519 br i1 %ballot_eq_zero, label %true, label %false520true:521 ret i32 42522false:523 ret i32 33524}525 526; Input that is not constant or direct result of a compare.527; Tests setting 0 to inactive lanes.528define amdgpu_ps void @non_cst_non_compare_input(ptr addrspace(1) %out, i32 %tid, i32 %cond) {529; GFX10-LABEL: non_cst_non_compare_input:530; GFX10: ; %bb.0: ; %entry531; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3532; GFX10-NEXT: ; implicit-def: $sgpr0533; GFX10-NEXT: s_and_saveexec_b32 s1, vcc_lo534; GFX10-NEXT: s_xor_b32 s1, exec_lo, s1535; GFX10-NEXT: ; %bb.1: ; %B536; GFX10-NEXT: v_cmp_gt_u32_e64 s0, 2, v2537; GFX10-NEXT: ; implicit-def: $vgpr2538; GFX10-NEXT: ; %bb.2: ; %Flow539; GFX10-NEXT: s_andn2_saveexec_b32 s1, s1540; GFX10-NEXT: ; %bb.3: ; %A541; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2542; GFX10-NEXT: s_andn2_b32 s0, s0, exec_lo543; GFX10-NEXT: s_and_b32 s2, vcc_lo, exec_lo544; GFX10-NEXT: s_or_b32 s0, s0, s2545; GFX10-NEXT: ; %bb.4: ; %exit546; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s1547; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0548; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v2549; GFX10-NEXT: v_mov_b32_e32 v2, s0550; GFX10-NEXT: global_store_dword v[0:1], v2, off551; GFX10-NEXT: s_endpgm552;553; GFX11-LABEL: non_cst_non_compare_input:554; GFX11: ; %bb.0: ; %entry555; GFX11-NEXT: s_mov_b32 s1, exec_lo556; GFX11-NEXT: ; implicit-def: $sgpr0557; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3558; GFX11-NEXT: s_xor_b32 s1, exec_lo, s1559; GFX11-NEXT: ; %bb.1: ; %B560; GFX11-NEXT: v_cmp_gt_u32_e64 s0, 2, v2561; GFX11-NEXT: ; implicit-def: $vgpr2562; GFX11-NEXT: ; %bb.2: ; %Flow563; GFX11-NEXT: s_and_not1_saveexec_b32 s1, s1564; GFX11-NEXT: ; %bb.3: ; %A565; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2566; GFX11-NEXT: s_and_not1_b32 s0, s0, exec_lo567; GFX11-NEXT: s_and_b32 s2, vcc_lo, exec_lo568; GFX11-NEXT: s_or_b32 s0, s0, s2569; GFX11-NEXT: ; %bb.4: ; %exit570; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s1571; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0572; GFX11-NEXT: v_cmp_ne_u32_e64 s0, 0, v2573; GFX11-NEXT: v_mov_b32_e32 v2, s0574; GFX11-NEXT: global_store_b32 v[0:1], v2, off575; GFX11-NEXT: s_endpgm576entry:577 %cmp = icmp eq i32 %cond, 0578 br i1 %cmp, label %A, label %B579 580A:581 %val_A = icmp uge i32 %tid, 1582 br label %exit583 584B:585 %val_B = icmp ult i32 %tid, 2586 br label %exit587 588exit:589 %phi = phi i1 [ %val_A, %A ], [ %val_B, %B ]590 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %phi)591 store i32 %ballot, ptr addrspace(1) %out592 ret void593}594 595define amdgpu_cs i32 @compare_bfloats(bfloat %x, bfloat %y) {596; GFX10-LABEL: compare_bfloats:597; GFX10: ; %bb.0:598; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1599; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0600; GFX10-NEXT: v_cmp_gt_f32_e64 s0, v0, v1601; GFX10-NEXT: ; return to shader part epilog602;603; GFX11-LABEL: compare_bfloats:604; GFX11: ; %bb.0:605; GFX11-NEXT: v_mov_b16_e32 v2.l, 0606; GFX11-NEXT: v_mov_b16_e32 v2.h, v1.l607; GFX11-NEXT: v_mov_b16_e32 v1.h, v0.l608; GFX11-NEXT: v_mov_b16_e32 v1.l, v2.l609; GFX11-NEXT: v_cmp_gt_f32_e64 s0, v1, v2610; GFX11-NEXT: ; return to shader part epilog611 %cmp = fcmp ogt bfloat %x, %y612 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %cmp)613 ret i32 %ballot614}615