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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s3 4declare i64 @llvm.amdgcn.ballot.i64(i1)5declare i64 @llvm.ctpop.i64(i64)6 7; Test ballot(0)8 9define amdgpu_cs i64 @constant_false() {10; CHECK-LABEL: constant_false:11; CHECK: ; %bb.0:12; CHECK-NEXT: s_mov_b32 s0, 013; CHECK-NEXT: s_mov_b32 s1, 014; CHECK-NEXT: ; return to shader part epilog15 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 0)16 ret i64 %ballot17}18 19; Test ballot(1)20 21define amdgpu_cs i64 @constant_true() {22; CHECK-LABEL: constant_true:23; CHECK: ; %bb.0:24; CHECK-NEXT: s_mov_b32 s0, exec_lo25; CHECK-NEXT: s_mov_b32 s1, exec_hi26; CHECK-NEXT: ; return to shader part epilog27 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 1)28 ret i64 %ballot29}30 31; Test ballot of a non-comparison operation32 33define amdgpu_cs i64 @non_compare(i32 %x) {34; CHECK-LABEL: non_compare:35; CHECK: ; %bb.0:36; CHECK-NEXT: v_and_b32_e32 v0, 1, v037; CHECK-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v038; CHECK-NEXT: ; return to shader part epilog39 %trunc = trunc i32 %x to i140 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %trunc)41 ret i64 %ballot42}43 44; Test ballot of comparisons45 46define amdgpu_cs i64 @compare_ints(i32 %x, i32 %y) {47; CHECK-LABEL: compare_ints:48; CHECK: ; %bb.0:49; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], v0, v150; CHECK-NEXT: ; return to shader part epilog51 %cmp = icmp eq i32 %x, %y52 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %cmp)53 ret i64 %ballot54}55 56define amdgpu_cs i64 @compare_int_with_constant(i32 %x) {57; CHECK-LABEL: compare_int_with_constant:58; CHECK: ; %bb.0:59; CHECK-NEXT: s_movk_i32 s0, 0x6260; CHECK-NEXT: v_cmp_lt_i32_e64 s[0:1], s0, v061; CHECK-NEXT: ; return to shader part epilog62 %cmp = icmp sge i32 %x, 9963 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %cmp)64 ret i64 %ballot65}66 67define amdgpu_cs i64 @compare_floats(float %x, float %y) {68; CHECK-LABEL: compare_floats:69; CHECK: ; %bb.0:70; CHECK-NEXT: v_cmp_gt_f32_e64 s[0:1], v0, v171; CHECK-NEXT: ; return to shader part epilog72 %cmp = fcmp ogt float %x, %y73 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %cmp)74 ret i64 %ballot75}76 77define amdgpu_cs i64 @ctpop_of_ballot(float %x, float %y) {78; CHECK-LABEL: ctpop_of_ballot:79; CHECK: ; %bb.0:80; CHECK-NEXT: v_cmp_gt_f32_e32 vcc, v0, v181; CHECK-NEXT: s_bcnt1_i32_b64 s0, vcc82; CHECK-NEXT: s_mov_b32 s1, 083; CHECK-NEXT: ; return to shader part epilog84 %cmp = fcmp ogt float %x, %y85 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %cmp)86 %bcnt = call i64 @llvm.ctpop.i64(i64 %ballot)87 ret i64 %bcnt88}89 90define amdgpu_cs i32 @branch_divergent_ballot_ne_zero_non_compare(i32 %v) {91; CHECK-LABEL: branch_divergent_ballot_ne_zero_non_compare:92; CHECK: ; %bb.0:93; CHECK-NEXT: v_and_b32_e32 v0, 1, v094; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v095; CHECK-NEXT: s_cbranch_vccz .LBB7_296; CHECK-NEXT: ; %bb.1: ; %true97; CHECK-NEXT: s_mov_b32 s0, 4298; CHECK-NEXT: s_branch .LBB7_399; CHECK-NEXT: .LBB7_2: ; %false100; CHECK-NEXT: s_mov_b32 s0, 33101; CHECK-NEXT: s_branch .LBB7_3102; CHECK-NEXT: .LBB7_3:103 %c = trunc i32 %v to i1104 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %c)105 %ballot_ne_zero = icmp ne i64 %ballot, 0106 br i1 %ballot_ne_zero, label %true, label %false107true:108 ret i32 42109false:110 ret i32 33111}112 113define amdgpu_cs i32 @branch_uniform_ballot_ne_zero_non_compare(i32 inreg %v) {114; CHECK-LABEL: branch_uniform_ballot_ne_zero_non_compare:115; CHECK: ; %bb.0:116; CHECK-NEXT: s_bitcmp0_b32 s0, 0117; CHECK-NEXT: s_cbranch_scc1 .LBB8_2118; CHECK-NEXT: ; %bb.1: ; %true119; CHECK-NEXT: s_mov_b32 s0, 42120; CHECK-NEXT: s_branch .LBB8_3121; CHECK-NEXT: .LBB8_2: ; %false122; CHECK-NEXT: s_mov_b32 s0, 33123; CHECK-NEXT: s_branch .LBB8_3124; CHECK-NEXT: .LBB8_3:125 %c = trunc i32 %v to i1126 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %c)127 %ballot_ne_zero = icmp ne i64 %ballot, 0128 br i1 %ballot_ne_zero, label %true, label %false129true:130 ret i32 42131false:132 ret i32 33133}134 135define amdgpu_cs i32 @branch_divergent_ballot_eq_zero_non_compare(i32 %v) {136; CHECK-LABEL: branch_divergent_ballot_eq_zero_non_compare:137; CHECK: ; %bb.0:138; CHECK-NEXT: v_and_b32_e32 v0, 1, v0139; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0140; CHECK-NEXT: s_cbranch_vccz .LBB9_2141; CHECK-NEXT: ; %bb.1: ; %false142; CHECK-NEXT: s_mov_b32 s0, 33143; CHECK-NEXT: s_branch .LBB9_3144; CHECK-NEXT: .LBB9_2: ; %true145; CHECK-NEXT: s_mov_b32 s0, 42146; CHECK-NEXT: s_branch .LBB9_3147; CHECK-NEXT: .LBB9_3:148 %c = trunc i32 %v to i1149 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %c)150 %ballot_eq_zero = icmp eq i64 %ballot, 0151 br i1 %ballot_eq_zero, label %true, label %false152true:153 ret i32 42154false:155 ret i32 33156}157 158define amdgpu_cs i32 @branch_uniform_ballot_eq_zero_non_compare(i32 inreg %v) {159; CHECK-LABEL: branch_uniform_ballot_eq_zero_non_compare:160; CHECK: ; %bb.0:161; CHECK-NEXT: s_bitcmp1_b32 s0, 0162; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0163; CHECK-NEXT: s_and_b64 vcc, exec, s[0:1]164; CHECK-NEXT: s_cbranch_vccnz .LBB10_2165; CHECK-NEXT: ; %bb.1: ; %true166; CHECK-NEXT: s_mov_b32 s0, 42167; CHECK-NEXT: s_branch .LBB10_3168; CHECK-NEXT: .LBB10_2: ; %false169; CHECK-NEXT: s_mov_b32 s0, 33170; CHECK-NEXT: s_branch .LBB10_3171; CHECK-NEXT: .LBB10_3:172 %c = trunc i32 %v to i1173 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %c)174 %ballot_eq_zero = icmp eq i64 %ballot, 0175 br i1 %ballot_eq_zero, label %true, label %false176true:177 ret i32 42178false:179 ret i32 33180}181 182define amdgpu_cs i32 @branch_divergent_ballot_ne_zero_compare(i32 %v) {183; CHECK-LABEL: branch_divergent_ballot_ne_zero_compare:184; CHECK: ; %bb.0:185; CHECK-NEXT: v_cmp_gt_u32_e32 vcc, 12, v0186; CHECK-NEXT: s_cbranch_vccz .LBB11_2187; CHECK-NEXT: ; %bb.1: ; %true188; CHECK-NEXT: s_mov_b32 s0, 42189; CHECK-NEXT: s_branch .LBB11_3190; CHECK-NEXT: .LBB11_2: ; %false191; CHECK-NEXT: s_mov_b32 s0, 33192; CHECK-NEXT: s_branch .LBB11_3193; CHECK-NEXT: .LBB11_3:194 %c = icmp ult i32 %v, 12195 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %c)196 %ballot_ne_zero = icmp ne i64 %ballot, 0197 br i1 %ballot_ne_zero, label %true, label %false198true:199 ret i32 42200false:201 ret i32 33202}203 204define amdgpu_cs i32 @branch_uniform_ballot_ne_zero_compare(i32 inreg %v) {205; CHECK-LABEL: branch_uniform_ballot_ne_zero_compare:206; CHECK: ; %bb.0:207; CHECK-NEXT: s_cmp_gt_u32 s0, 11208; CHECK-NEXT: s_cbranch_scc1 .LBB12_2209; CHECK-NEXT: ; %bb.1: ; %true210; CHECK-NEXT: s_mov_b32 s0, 42211; CHECK-NEXT: s_branch .LBB12_3212; CHECK-NEXT: .LBB12_2: ; %false213; CHECK-NEXT: s_mov_b32 s0, 33214; CHECK-NEXT: s_branch .LBB12_3215; CHECK-NEXT: .LBB12_3:216 %c = icmp ult i32 %v, 12217 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %c)218 %ballot_ne_zero = icmp ne i64 %ballot, 0219 br i1 %ballot_ne_zero, label %true, label %false220true:221 ret i32 42222false:223 ret i32 33224}225 226define amdgpu_cs i32 @branch_divergent_ballot_eq_zero_compare(i32 %v) {227; CHECK-LABEL: branch_divergent_ballot_eq_zero_compare:228; CHECK: ; %bb.0:229; CHECK-NEXT: v_cmp_gt_u32_e32 vcc, 12, v0230; CHECK-NEXT: s_cbranch_vccz .LBB13_2231; CHECK-NEXT: ; %bb.1: ; %false232; CHECK-NEXT: s_mov_b32 s0, 33233; CHECK-NEXT: s_branch .LBB13_3234; CHECK-NEXT: .LBB13_2: ; %true235; CHECK-NEXT: s_mov_b32 s0, 42236; CHECK-NEXT: s_branch .LBB13_3237; CHECK-NEXT: .LBB13_3:238 %c = icmp ult i32 %v, 12239 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %c)240 %ballot_eq_zero = icmp eq i64 %ballot, 0241 br i1 %ballot_eq_zero, label %true, label %false242true:243 ret i32 42244false:245 ret i32 33246}247 248define amdgpu_cs i32 @branch_uniform_ballot_eq_zero_compare(i32 inreg %v) {249; CHECK-LABEL: branch_uniform_ballot_eq_zero_compare:250; CHECK: ; %bb.0:251; CHECK-NEXT: s_cmp_lt_u32 s0, 12252; CHECK-NEXT: s_cbranch_scc1 .LBB14_2253; CHECK-NEXT: ; %bb.1: ; %true254; CHECK-NEXT: s_mov_b32 s0, 42255; CHECK-NEXT: s_branch .LBB14_3256; CHECK-NEXT: .LBB14_2: ; %false257; CHECK-NEXT: s_mov_b32 s0, 33258; CHECK-NEXT: s_branch .LBB14_3259; CHECK-NEXT: .LBB14_3:260 %c = icmp ult i32 %v, 12261 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %c)262 %ballot_eq_zero = icmp eq i64 %ballot, 0263 br i1 %ballot_eq_zero, label %true, label %false264true:265 ret i32 42266false:267 ret i32 33268}269 270define amdgpu_cs i32 @branch_divergent_ballot_ne_zero_and(i32 %v1, i32 %v2) {271; CHECK-LABEL: branch_divergent_ballot_ne_zero_and:272; CHECK: ; %bb.0:273; CHECK-NEXT: v_cmp_gt_u32_e32 vcc, 12, v0274; CHECK-NEXT: v_cmp_lt_u32_e64 s[0:1], 34, v1275; CHECK-NEXT: s_and_b64 vcc, vcc, s[0:1]276; CHECK-NEXT: s_cbranch_vccz .LBB15_2277; CHECK-NEXT: ; %bb.1: ; %true278; CHECK-NEXT: s_mov_b32 s0, 42279; CHECK-NEXT: s_branch .LBB15_3280; CHECK-NEXT: .LBB15_2: ; %false281; CHECK-NEXT: s_mov_b32 s0, 33282; CHECK-NEXT: s_branch .LBB15_3283; CHECK-NEXT: .LBB15_3:284 %v1c = icmp ult i32 %v1, 12285 %v2c = icmp ugt i32 %v2, 34286 %c = and i1 %v1c, %v2c287 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %c)288 %ballot_ne_zero = icmp ne i64 %ballot, 0289 br i1 %ballot_ne_zero, label %true, label %false290true:291 ret i32 42292false:293 ret i32 33294}295 296define amdgpu_cs i32 @branch_uniform_ballot_ne_zero_and(i32 inreg %v1, i32 inreg %v2) {297; CHECK-LABEL: branch_uniform_ballot_ne_zero_and:298; CHECK: ; %bb.0:299; CHECK-NEXT: s_cmp_gt_u32 s0, 11300; CHECK-NEXT: s_cselect_b64 s[2:3], -1, 0301; CHECK-NEXT: s_cmp_lt_u32 s1, 35302; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0303; CHECK-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]304; CHECK-NEXT: s_and_b64 vcc, exec, s[0:1]305; CHECK-NEXT: s_cbranch_vccnz .LBB16_2306; CHECK-NEXT: ; %bb.1: ; %true307; CHECK-NEXT: s_mov_b32 s0, 42308; CHECK-NEXT: s_branch .LBB16_3309; CHECK-NEXT: .LBB16_2: ; %false310; CHECK-NEXT: s_mov_b32 s0, 33311; CHECK-NEXT: s_branch .LBB16_3312; CHECK-NEXT: .LBB16_3:313 %v1c = icmp ult i32 %v1, 12314 %v2c = icmp ugt i32 %v2, 34315 %c = and i1 %v1c, %v2c316 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %c)317 %ballot_ne_zero = icmp ne i64 %ballot, 0318 br i1 %ballot_ne_zero, label %true, label %false319true:320 ret i32 42321false:322 ret i32 33323}324 325define amdgpu_cs i32 @branch_divergent_ballot_eq_zero_and(i32 %v1, i32 %v2) {326; CHECK-LABEL: branch_divergent_ballot_eq_zero_and:327; CHECK: ; %bb.0:328; CHECK-NEXT: v_cmp_gt_u32_e32 vcc, 12, v0329; CHECK-NEXT: v_cmp_lt_u32_e64 s[0:1], 34, v1330; CHECK-NEXT: s_and_b64 vcc, vcc, s[0:1]331; CHECK-NEXT: s_cbranch_vccz .LBB17_2332; CHECK-NEXT: ; %bb.1: ; %false333; CHECK-NEXT: s_mov_b32 s0, 33334; CHECK-NEXT: s_branch .LBB17_3335; CHECK-NEXT: .LBB17_2: ; %true336; CHECK-NEXT: s_mov_b32 s0, 42337; CHECK-NEXT: s_branch .LBB17_3338; CHECK-NEXT: .LBB17_3:339 %v1c = icmp ult i32 %v1, 12340 %v2c = icmp ugt i32 %v2, 34341 %c = and i1 %v1c, %v2c342 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %c)343 %ballot_eq_zero = icmp eq i64 %ballot, 0344 br i1 %ballot_eq_zero, label %true, label %false345true:346 ret i32 42347false:348 ret i32 33349}350 351define amdgpu_cs i32 @branch_uniform_ballot_eq_zero_and(i32 inreg %v1, i32 inreg %v2) {352; CHECK-LABEL: branch_uniform_ballot_eq_zero_and:353; CHECK: ; %bb.0:354; CHECK-NEXT: s_cmp_lt_u32 s0, 12355; CHECK-NEXT: s_cselect_b64 s[2:3], -1, 0356; CHECK-NEXT: s_cmp_gt_u32 s1, 34357; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0358; CHECK-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]359; CHECK-NEXT: s_and_b64 vcc, exec, s[0:1]360; CHECK-NEXT: s_cbranch_vccnz .LBB18_2361; CHECK-NEXT: ; %bb.1: ; %true362; CHECK-NEXT: s_mov_b32 s0, 42363; CHECK-NEXT: s_branch .LBB18_3364; CHECK-NEXT: .LBB18_2: ; %false365; CHECK-NEXT: s_mov_b32 s0, 33366; CHECK-NEXT: s_branch .LBB18_3367; CHECK-NEXT: .LBB18_3:368 %v1c = icmp ult i32 %v1, 12369 %v2c = icmp ugt i32 %v2, 34370 %c = and i1 %v1c, %v2c371 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %c)372 %ballot_eq_zero = icmp eq i64 %ballot, 0373 br i1 %ballot_eq_zero, label %true, label %false374true:375 ret i32 42376false:377 ret i32 33378}379 380define amdgpu_cs i32 @branch_uniform_ballot_sgt_N_compare(i32 inreg %v) {381; CHECK-LABEL: branch_uniform_ballot_sgt_N_compare:382; CHECK: ; %bb.0:383; CHECK-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, 12384; CHECK-NEXT: v_cmp_lt_i64_e64 vcc, s[0:1], 23385; CHECK-NEXT: s_cbranch_vccnz .LBB19_2386; CHECK-NEXT: ; %bb.1: ; %true387; CHECK-NEXT: s_mov_b32 s0, 42388; CHECK-NEXT: s_branch .LBB19_3389; CHECK-NEXT: .LBB19_2: ; %false390; CHECK-NEXT: s_mov_b32 s0, 33391; CHECK-NEXT: s_branch .LBB19_3392; CHECK-NEXT: .LBB19_3:393 %c = icmp ult i32 %v, 12394 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %c)395 %bc = icmp sgt i64 %ballot, 22396 br i1 %bc, label %true, label %false397true:398 ret i32 42399false:400 ret i32 33401}402 403declare i64 @llvm.amdgcn.icmp.i64(i1, i1, i32)404 405define amdgpu_cs i32 @branch_divergent_simulated_negated_ballot_ne_zero_and(i32 %v1, i32 %v2) {406; CHECK-LABEL: branch_divergent_simulated_negated_ballot_ne_zero_and:407; CHECK: ; %bb.0:408; CHECK-NEXT: v_cmp_gt_u32_e32 vcc, 12, v0409; CHECK-NEXT: v_cmp_lt_u32_e64 s[0:1], 34, v1410; CHECK-NEXT: s_and_b64 vcc, vcc, s[0:1]411; CHECK-NEXT: s_cbranch_vccnz .LBB20_2412; CHECK-NEXT: ; %bb.1: ; %true413; CHECK-NEXT: s_mov_b32 s0, 42414; CHECK-NEXT: s_branch .LBB20_3415; CHECK-NEXT: .LBB20_2: ; %false416; CHECK-NEXT: s_mov_b32 s0, 33417; CHECK-NEXT: s_branch .LBB20_3418; CHECK-NEXT: .LBB20_3:419 %v1c = icmp ult i32 %v1, 12420 %v2c = icmp ugt i32 %v2, 34421 %c = and i1 %v1c, %v2c422 %ballot = call i64 @llvm.amdgcn.icmp.i64(i1 %c, i1 0, i32 32) ; ICMP_EQ == 32423 %ballot_ne_zero = icmp ne i64 %ballot, 0424 br i1 %ballot_ne_zero, label %true, label %false425true:426 ret i32 42427false:428 ret i32 33429}430 431define amdgpu_cs i32 @branch_uniform_simulated_negated_ballot_ne_zero_and(i32 inreg %v1, i32 inreg %v2) {432; CHECK-LABEL: branch_uniform_simulated_negated_ballot_ne_zero_and:433; CHECK: ; %bb.0:434; CHECK-NEXT: s_cmp_lt_u32 s0, 12435; CHECK-NEXT: s_cselect_b64 s[2:3], -1, 0436; CHECK-NEXT: s_cmp_gt_u32 s1, 34437; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0438; CHECK-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]439; CHECK-NEXT: s_and_b64 s[0:1], s[0:1], exec440; CHECK-NEXT: s_cbranch_scc1 .LBB21_2441; CHECK-NEXT: ; %bb.1: ; %true442; CHECK-NEXT: s_mov_b32 s0, 42443; CHECK-NEXT: s_branch .LBB21_3444; CHECK-NEXT: .LBB21_2: ; %false445; CHECK-NEXT: s_mov_b32 s0, 33446; CHECK-NEXT: s_branch .LBB21_3447; CHECK-NEXT: .LBB21_3:448 %v1c = icmp ult i32 %v1, 12449 %v2c = icmp ugt i32 %v2, 34450 %c = and i1 %v1c, %v2c451 %ballot = call i64 @llvm.amdgcn.icmp.i64(i1 %c, i1 0, i32 32) ; ICMP_EQ == 32452 %ballot_ne_zero = icmp ne i64 %ballot, 0453 br i1 %ballot_ne_zero, label %true, label %false454true:455 ret i32 42456false:457 ret i32 33458}459 460define amdgpu_cs i32 @branch_divergent_simulated_negated_ballot_eq_zero_and(i32 %v1, i32 %v2) {461; CHECK-LABEL: branch_divergent_simulated_negated_ballot_eq_zero_and:462; CHECK: ; %bb.0:463; CHECK-NEXT: v_cmp_gt_u32_e32 vcc, 12, v0464; CHECK-NEXT: v_cmp_lt_u32_e64 s[0:1], 34, v1465; CHECK-NEXT: s_and_b64 vcc, vcc, s[0:1]466; CHECK-NEXT: s_cbranch_vccnz .LBB22_2467; CHECK-NEXT: ; %bb.1: ; %false468; CHECK-NEXT: s_mov_b32 s0, 33469; CHECK-NEXT: s_branch .LBB22_3470; CHECK-NEXT: .LBB22_2: ; %true471; CHECK-NEXT: s_mov_b32 s0, 42472; CHECK-NEXT: s_branch .LBB22_3473; CHECK-NEXT: .LBB22_3:474 %v1c = icmp ult i32 %v1, 12475 %v2c = icmp ugt i32 %v2, 34476 %c = and i1 %v1c, %v2c477 %ballot = call i64 @llvm.amdgcn.icmp.i64(i1 %c, i1 0, i32 32) ; ICMP_EQ == 32478 %ballot_eq_zero = icmp eq i64 %ballot, 0479 br i1 %ballot_eq_zero, label %true, label %false480true:481 ret i32 42482false:483 ret i32 33484}485 486define amdgpu_cs i32 @branch_uniform_simulated_negated_ballot_eq_zero_and(i32 inreg %v1, i32 inreg %v2) {487; CHECK-LABEL: branch_uniform_simulated_negated_ballot_eq_zero_and:488; CHECK: ; %bb.0:489; CHECK-NEXT: s_cmp_lt_u32 s0, 12490; CHECK-NEXT: s_cselect_b64 s[2:3], -1, 0491; CHECK-NEXT: s_cmp_gt_u32 s1, 34492; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0493; CHECK-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]494; CHECK-NEXT: s_and_b64 s[0:1], s[0:1], exec495; CHECK-NEXT: s_cbranch_scc1 .LBB23_2496; CHECK-NEXT: ; %bb.1: ; %false497; CHECK-NEXT: s_mov_b32 s0, 33498; CHECK-NEXT: s_branch .LBB23_3499; CHECK-NEXT: .LBB23_2: ; %true500; CHECK-NEXT: s_mov_b32 s0, 42501; CHECK-NEXT: s_branch .LBB23_3502; CHECK-NEXT: .LBB23_3:503 %v1c = icmp ult i32 %v1, 12504 %v2c = icmp ugt i32 %v2, 34505 %c = and i1 %v1c, %v2c506 %ballot = call i64 @llvm.amdgcn.icmp.i64(i1 %c, i1 0, i32 32) ; ICMP_EQ == 32507 %ballot_eq_zero = icmp eq i64 %ballot, 0508 br i1 %ballot_eq_zero, label %true, label %false509true:510 ret i32 42511false:512 ret i32 33513}514 515; Input that is not constant or direct result of a compare.516; Tests setting 0 to inactive lanes.517define amdgpu_ps void @non_cst_non_compare_input(ptr addrspace(1) %out, i32 %tid, i32 %cond) {518; CHECK-LABEL: non_cst_non_compare_input:519; CHECK: ; %bb.0: ; %entry520; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3521; CHECK-NEXT: ; implicit-def: $sgpr0_sgpr1522; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc523; CHECK-NEXT: s_xor_b64 s[2:3], exec, s[2:3]524; CHECK-NEXT: ; %bb.1: ; %B525; CHECK-NEXT: v_cmp_gt_u32_e64 s[0:1], 2, v2526; CHECK-NEXT: ; implicit-def: $vgpr2527; CHECK-NEXT: ; %bb.2: ; %Flow528; CHECK-NEXT: s_andn2_saveexec_b64 s[2:3], s[2:3]529; CHECK-NEXT: ; %bb.3: ; %A530; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2531; CHECK-NEXT: s_andn2_b64 s[0:1], s[0:1], exec532; CHECK-NEXT: s_and_b64 s[4:5], vcc, exec533; CHECK-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]534; CHECK-NEXT: ; %bb.4: ; %exit535; CHECK-NEXT: s_or_b64 exec, exec, s[2:3]536; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]537; CHECK-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2538; CHECK-NEXT: v_mov_b32_e32 v3, s1539; CHECK-NEXT: v_mov_b32_e32 v2, s0540; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off541; CHECK-NEXT: s_endpgm542entry:543 %cmp = icmp eq i32 %cond, 0544 br i1 %cmp, label %A, label %B545 546A:547 %val_A = icmp uge i32 %tid, 1548 br label %exit549 550B:551 %val_B = icmp ult i32 %tid, 2552 br label %exit553 554exit:555 %phi = phi i1 [ %val_A, %A ], [ %val_B, %B ]556 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %phi)557 store i64 %ballot, ptr addrspace(1) %out558 ret void559}560 561define amdgpu_cs i64 @compare_bfloats(bfloat %x, bfloat %y) {562; CHECK-LABEL: compare_bfloats:563; CHECK: ; %bb.0:564; CHECK-NEXT: v_lshlrev_b32_e32 v1, 16, v1565; CHECK-NEXT: v_lshlrev_b32_e32 v0, 16, v0566; CHECK-NEXT: v_cmp_gt_f32_e64 s[0:1], v0, v1567; CHECK-NEXT: ; return to shader part epilog568 %cmp = fcmp ogt bfloat %x, %y569 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %cmp)570 ret i64 %ballot571}572