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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX950,GFX950-SDAG %s3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX950,GFX950-GISEL %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-SDAG,GFX1250-TRUE16,GFX1250-SDG-TRUE16 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-SDAG,GFX1250-FAKE16,GFX1250-SDG-FAKE16 %s6; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-GISEL,GFX1250-TRUE16,GFX1250-GISEL-TRUE16 %s7; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-GISEL,GFX1250-FAKE16,GFX1250-GISEL-FAKE16 %s8 9declare i32 @llvm.amdgcn.bitop3.i32(i32, i32, i32, i32)10declare i16 @llvm.amdgcn.bitop3.i16(i16, i16, i16, i32)11 12define amdgpu_ps float @bitop3_b32_vvv(i32 %a, i32 %b, i32 %c) {13; GFX950-LABEL: bitop3_b32_vvv:14; GFX950: ; %bb.0:15; GFX950-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0xf16; GFX950-NEXT: ; return to shader part epilog17;18; GFX1250-LABEL: bitop3_b32_vvv:19; GFX1250: ; %bb.0:20; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 121; GFX1250-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0xf22; GFX1250-NEXT: ; return to shader part epilog23 %ret = call i32 @llvm.amdgcn.bitop3.i32(i32 %a, i32 %b, i32 %c, i32 15)24 %ret_cast = bitcast i32 %ret to float25 ret float %ret_cast26}27 28define amdgpu_ps float @bitop3_b32_svv(i32 inreg %a, i32 %b, i32 %c) {29; GFX950-LABEL: bitop3_b32_svv:30; GFX950: ; %bb.0:31; GFX950-NEXT: v_bitop3_b32 v0, s0, v0, v1 bitop3:0x1032; GFX950-NEXT: ; return to shader part epilog33;34; GFX1250-LABEL: bitop3_b32_svv:35; GFX1250: ; %bb.0:36; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 137; GFX1250-NEXT: v_bitop3_b32 v0, s0, v0, v1 bitop3:0x1038; GFX1250-NEXT: ; return to shader part epilog39 %ret = call i32 @llvm.amdgcn.bitop3.i32(i32 %a, i32 %b, i32 %c, i32 16)40 %ret_cast = bitcast i32 %ret to float41 ret float %ret_cast42}43 44define amdgpu_ps float @bitop3_b32_ssv(i32 inreg %a, i32 inreg %b, i32 %c) {45; GFX950-LABEL: bitop3_b32_ssv:46; GFX950: ; %bb.0:47; GFX950-NEXT: v_mov_b32_e32 v1, s148; GFX950-NEXT: v_bitop3_b32 v0, s0, v1, v0 bitop3:0x1149; GFX950-NEXT: ; return to shader part epilog50;51; GFX1250-LABEL: bitop3_b32_ssv:52; GFX1250: ; %bb.0:53; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 154; GFX1250-NEXT: v_bitop3_b32 v0, s0, s1, v0 bitop3:0x1155; GFX1250-NEXT: ; return to shader part epilog56 %ret = call i32 @llvm.amdgcn.bitop3.i32(i32 %a, i32 %b, i32 %c, i32 17)57 %ret_cast = bitcast i32 %ret to float58 ret float %ret_cast59}60 61define amdgpu_ps float @bitop3_b32_sss(i32 inreg %a, i32 inreg %b, i32 inreg %c) {62; GFX950-LABEL: bitop3_b32_sss:63; GFX950: ; %bb.0:64; GFX950-NEXT: v_mov_b32_e32 v0, s165; GFX950-NEXT: v_mov_b32_e32 v1, s266; GFX950-NEXT: v_bitop3_b32 v0, s0, v0, v1 bitop3:0x1267; GFX950-NEXT: ; return to shader part epilog68;69; GFX1250-LABEL: bitop3_b32_sss:70; GFX1250: ; %bb.0:71; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 172; GFX1250-NEXT: v_mov_b32_e32 v0, s273; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)74; GFX1250-NEXT: v_bitop3_b32 v0, s0, s1, v0 bitop3:0x1275; GFX1250-NEXT: ; return to shader part epilog76 %ret = call i32 @llvm.amdgcn.bitop3.i32(i32 %a, i32 %b, i32 %c, i32 18)77 %ret_cast = bitcast i32 %ret to float78 ret float %ret_cast79}80 81define amdgpu_ps float @bitop3_b32_vvi(i32 %a, i32 %b) {82; GFX950-SDAG-LABEL: bitop3_b32_vvi:83; GFX950-SDAG: ; %bb.0:84; GFX950-SDAG-NEXT: s_movk_i32 s0, 0x3e885; GFX950-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, s0 bitop3:0x1386; GFX950-SDAG-NEXT: ; return to shader part epilog87;88; GFX950-GISEL-LABEL: bitop3_b32_vvi:89; GFX950-GISEL: ; %bb.0:90; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e891; GFX950-GISEL-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x1392; GFX950-GISEL-NEXT: ; return to shader part epilog93;94; GFX1250-LABEL: bitop3_b32_vvi:95; GFX1250: ; %bb.0:96; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 197; GFX1250-NEXT: v_bitop3_b32 v0, v0, v1, 0x3e8 bitop3:0x1398; GFX1250-NEXT: ; return to shader part epilog99 %ret = call i32 @llvm.amdgcn.bitop3.i32(i32 %a, i32 %b, i32 1000, i32 19)100 %ret_cast = bitcast i32 %ret to float101 ret float %ret_cast102}103 104define amdgpu_ps float @bitop3_b32_vii(i32 %a) {105; GFX950-SDAG-LABEL: bitop3_b32_vii:106; GFX950-SDAG: ; %bb.0:107; GFX950-SDAG-NEXT: s_movk_i32 s0, 0x7d0108; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0x3e8109; GFX950-SDAG-NEXT: v_bitop3_b32 v0, v0, s0, v1 bitop3:0x14110; GFX950-SDAG-NEXT: ; return to shader part epilog111;112; GFX950-GISEL-LABEL: bitop3_b32_vii:113; GFX950-GISEL: ; %bb.0:114; GFX950-GISEL-NEXT: v_mov_b32_e32 v1, 0x7d0115; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e8116; GFX950-GISEL-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x14117; GFX950-GISEL-NEXT: ; return to shader part epilog118;119; GFX1250-SDAG-LABEL: bitop3_b32_vii:120; GFX1250-SDAG: ; %bb.0:121; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1122; GFX1250-SDAG-NEXT: s_movk_i32 s0, 0x7d0123; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)124; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, s0, 0x3e8 bitop3:0x14125; GFX1250-SDAG-NEXT: ; return to shader part epilog126;127; GFX1250-GISEL-LABEL: bitop3_b32_vii:128; GFX1250-GISEL: ; %bb.0:129; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1130; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e8131; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)132; GFX1250-GISEL-NEXT: v_bitop3_b32 v0, v0, 0x7d0, v1 bitop3:0x14133; GFX1250-GISEL-NEXT: ; return to shader part epilog134 %ret = call i32 @llvm.amdgcn.bitop3.i32(i32 %a, i32 2000, i32 1000, i32 20)135 %ret_cast = bitcast i32 %ret to float136 ret float %ret_cast137}138 139; FIXME: Constant fold this140 141define amdgpu_ps float @bitop3_b32_iii() {142; GFX950-SDAG-LABEL: bitop3_b32_iii:143; GFX950-SDAG: ; %bb.0:144; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xbb8145; GFX950-SDAG-NEXT: v_mov_b32_e32 v0, 0x7d0146; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0x3e8147; GFX950-SDAG-NEXT: v_bitop3_b32 v0, s0, v0, v1 bitop3:0x15148; GFX950-SDAG-NEXT: ; return to shader part epilog149;150; GFX950-GISEL-LABEL: bitop3_b32_iii:151; GFX950-GISEL: ; %bb.0:152; GFX950-GISEL-NEXT: v_mov_b32_e32 v0, 0xbb8153; GFX950-GISEL-NEXT: v_mov_b32_e32 v1, 0x7d0154; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e8155; GFX950-GISEL-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x15156; GFX950-GISEL-NEXT: ; return to shader part epilog157;158; GFX1250-SDAG-LABEL: bitop3_b32_iii:159; GFX1250-SDAG: ; %bb.0:160; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1161; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, 0x3e8162; GFX1250-SDAG-NEXT: s_movk_i32 s0, 0xbb8163; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)164; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, s0, 0x7d0, v0 bitop3:0x15165; GFX1250-SDAG-NEXT: ; return to shader part epilog166;167; GFX1250-GISEL-LABEL: bitop3_b32_iii:168; GFX1250-GISEL: ; %bb.0:169; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1170; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, 0x7d0171; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e8172; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)173; GFX1250-GISEL-NEXT: v_bitop3_b32 v0, 0xbb8, v0, v1 bitop3:0x15174; GFX1250-GISEL-NEXT: ; return to shader part epilog175 %ret = call i32 @llvm.amdgcn.bitop3.i32(i32 3000, i32 2000, i32 1000, i32 21)176 %ret_cast = bitcast i32 %ret to float177 ret float %ret_cast178}179 180define amdgpu_ps half @bitop3_b16_vvv(i16 %a, i16 %b, i16 %c) {181; GFX950-LABEL: bitop3_b16_vvv:182; GFX950: ; %bb.0:183; GFX950-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:0xf184; GFX950-NEXT: ; return to shader part epilog185;186; GFX1250-TRUE16-LABEL: bitop3_b16_vvv:187; GFX1250-TRUE16: ; %bb.0:188; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1189; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:0xf190; GFX1250-TRUE16-NEXT: ; return to shader part epilog191;192; GFX1250-FAKE16-LABEL: bitop3_b16_vvv:193; GFX1250-FAKE16: ; %bb.0:194; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1195; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:0xf196; GFX1250-FAKE16-NEXT: ; return to shader part epilog197 %ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 %b, i16 %c, i32 15)198 %ret_cast = bitcast i16 %ret to half199 ret half %ret_cast200}201 202define amdgpu_ps half @bitop3_b16_svv(i16 inreg %a, i16 %b, i16 %c) {203; GFX950-LABEL: bitop3_b16_svv:204; GFX950: ; %bb.0:205; GFX950-NEXT: v_bitop3_b16 v0, s0, v0, v1 bitop3:0x10206; GFX950-NEXT: ; return to shader part epilog207;208; GFX1250-TRUE16-LABEL: bitop3_b16_svv:209; GFX1250-TRUE16: ; %bb.0:210; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1211; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, v0.l, v1.l bitop3:0x10212; GFX1250-TRUE16-NEXT: ; return to shader part epilog213;214; GFX1250-FAKE16-LABEL: bitop3_b16_svv:215; GFX1250-FAKE16: ; %bb.0:216; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1217; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, s0, v0, v1 bitop3:0x10218; GFX1250-FAKE16-NEXT: ; return to shader part epilog219 %ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 %b, i16 %c, i32 16)220 %ret_cast = bitcast i16 %ret to half221 ret half %ret_cast222}223 224define amdgpu_ps half @bitop3_b16_ssv(i16 inreg %a, i16 inreg %b, i16 %c) {225; GFX950-LABEL: bitop3_b16_ssv:226; GFX950: ; %bb.0:227; GFX950-NEXT: v_mov_b32_e32 v1, s1228; GFX950-NEXT: v_bitop3_b16 v0, s0, v1, v0 bitop3:0x11229; GFX950-NEXT: ; return to shader part epilog230;231; GFX1250-TRUE16-LABEL: bitop3_b16_ssv:232; GFX1250-TRUE16: ; %bb.0:233; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1234; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, s1, v0.l bitop3:0x11235; GFX1250-TRUE16-NEXT: ; return to shader part epilog236;237; GFX1250-FAKE16-LABEL: bitop3_b16_ssv:238; GFX1250-FAKE16: ; %bb.0:239; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1240; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, s0, s1, v0 bitop3:0x11241; GFX1250-FAKE16-NEXT: ; return to shader part epilog242 %ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 %b, i16 %c, i32 17)243 %ret_cast = bitcast i16 %ret to half244 ret half %ret_cast245}246 247define amdgpu_ps half @bitop3_b16_sss(i16 inreg %a, i16 inreg %b, i16 inreg %c) {248; GFX950-LABEL: bitop3_b16_sss:249; GFX950: ; %bb.0:250; GFX950-NEXT: v_mov_b32_e32 v0, s1251; GFX950-NEXT: v_mov_b32_e32 v1, s2252; GFX950-NEXT: v_bitop3_b16 v0, s0, v0, v1 bitop3:0x12253; GFX950-NEXT: ; return to shader part epilog254;255; GFX1250-TRUE16-LABEL: bitop3_b16_sss:256; GFX1250-TRUE16: ; %bb.0:257; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1258; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2259; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)260; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, s1, v0.l bitop3:0x12261; GFX1250-TRUE16-NEXT: ; return to shader part epilog262;263; GFX1250-FAKE16-LABEL: bitop3_b16_sss:264; GFX1250-FAKE16: ; %bb.0:265; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1266; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, s2267; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)268; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, s0, s1, v0 bitop3:0x12269; GFX1250-FAKE16-NEXT: ; return to shader part epilog270 %ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 %b, i16 %c, i32 18)271 %ret_cast = bitcast i16 %ret to half272 ret half %ret_cast273}274 275define amdgpu_ps half @bitop3_b16_vvi(i16 %a, i16 %b) {276; GFX950-SDAG-LABEL: bitop3_b16_vvi:277; GFX950-SDAG: ; %bb.0:278; GFX950-SDAG-NEXT: s_movk_i32 s0, 0x3e8279; GFX950-SDAG-NEXT: v_bitop3_b16 v0, v0, v1, s0 bitop3:0x13280; GFX950-SDAG-NEXT: ; return to shader part epilog281;282; GFX950-GISEL-LABEL: bitop3_b16_vvi:283; GFX950-GISEL: ; %bb.0:284; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e8285; GFX950-GISEL-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:0x13286; GFX950-GISEL-NEXT: ; return to shader part epilog287;288; GFX1250-TRUE16-LABEL: bitop3_b16_vvi:289; GFX1250-TRUE16: ; %bb.0:290; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1291; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, 0x3e8 bitop3:0x13292; GFX1250-TRUE16-NEXT: ; return to shader part epilog293;294; GFX1250-FAKE16-LABEL: bitop3_b16_vvi:295; GFX1250-FAKE16: ; %bb.0:296; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1297; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, 0x3e8 bitop3:0x13298; GFX1250-FAKE16-NEXT: ; return to shader part epilog299 %ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 %b, i16 1000, i32 19)300 %ret_cast = bitcast i16 %ret to half301 ret half %ret_cast302}303 304define amdgpu_ps half @bitop3_b16_vii(i16 %a) {305; GFX950-SDAG-LABEL: bitop3_b16_vii:306; GFX950-SDAG: ; %bb.0:307; GFX950-SDAG-NEXT: s_movk_i32 s0, 0x7d0308; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0x3e8309; GFX950-SDAG-NEXT: v_bitop3_b16 v0, v0, s0, v1 bitop3:0x14310; GFX950-SDAG-NEXT: ; return to shader part epilog311;312; GFX950-GISEL-LABEL: bitop3_b16_vii:313; GFX950-GISEL: ; %bb.0:314; GFX950-GISEL-NEXT: v_mov_b32_e32 v1, 0x7d0315; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e8316; GFX950-GISEL-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:0x14317; GFX950-GISEL-NEXT: ; return to shader part epilog318;319; GFX1250-SDG-TRUE16-LABEL: bitop3_b16_vii:320; GFX1250-SDG-TRUE16: ; %bb.0:321; GFX1250-SDG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1322; GFX1250-SDG-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0x7d0323; GFX1250-SDG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)324; GFX1250-SDG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, 0x3e8 bitop3:0x14325; GFX1250-SDG-TRUE16-NEXT: ; return to shader part epilog326;327; GFX1250-SDG-FAKE16-LABEL: bitop3_b16_vii:328; GFX1250-SDG-FAKE16: ; %bb.0:329; GFX1250-SDG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1330; GFX1250-SDG-FAKE16-NEXT: s_movk_i32 s0, 0x7d0331; GFX1250-SDG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)332; GFX1250-SDG-FAKE16-NEXT: v_bitop3_b16 v0, v0, s0, 0x3e8 bitop3:0x14333; GFX1250-SDG-FAKE16-NEXT: ; return to shader part epilog334;335; GFX1250-GISEL-TRUE16-LABEL: bitop3_b16_vii:336; GFX1250-GISEL-TRUE16: ; %bb.0:337; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1338; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0x3e8339; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)340; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, 0x7d0, v0.h bitop3:0x14341; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog342;343; GFX1250-GISEL-FAKE16-LABEL: bitop3_b16_vii:344; GFX1250-GISEL-FAKE16: ; %bb.0:345; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1346; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0x3e8347; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)348; GFX1250-GISEL-FAKE16-NEXT: v_bitop3_b16 v0, v0, 0x7d0, v1 bitop3:0x14349; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog350 %ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 2000, i16 1000, i32 20)351 %ret_cast = bitcast i16 %ret to half352 ret half %ret_cast353}354 355; FIXME: Constant fold this356define amdgpu_ps half @bitop3_b16_iii() {357; GFX950-SDAG-LABEL: bitop3_b16_iii:358; GFX950-SDAG: ; %bb.0:359; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xbb8360; GFX950-SDAG-NEXT: v_mov_b32_e32 v0, 0x7d0361; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0x3e8362; GFX950-SDAG-NEXT: v_bitop3_b16 v0, s0, v0, v1 bitop3:0x15363; GFX950-SDAG-NEXT: ; return to shader part epilog364;365; GFX950-GISEL-LABEL: bitop3_b16_iii:366; GFX950-GISEL: ; %bb.0:367; GFX950-GISEL-NEXT: v_mov_b32_e32 v0, 0xbb8368; GFX950-GISEL-NEXT: v_mov_b32_e32 v1, 0x7d0369; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e8370; GFX950-GISEL-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:0x15371; GFX950-GISEL-NEXT: ; return to shader part epilog372;373; GFX1250-SDG-TRUE16-LABEL: bitop3_b16_iii:374; GFX1250-SDG-TRUE16: ; %bb.0:375; GFX1250-SDG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1376; GFX1250-SDG-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x7d0377; GFX1250-SDG-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0xbb8378; GFX1250-SDG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)379; GFX1250-SDG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.h, v0.l, 0x3e8 bitop3:0x15380; GFX1250-SDG-TRUE16-NEXT: ; return to shader part epilog381;382; GFX1250-SDG-FAKE16-LABEL: bitop3_b16_iii:383; GFX1250-SDG-FAKE16: ; %bb.0:384; GFX1250-SDG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1385; GFX1250-SDG-FAKE16-NEXT: v_mov_b32_e32 v0, 0x3e8386; GFX1250-SDG-FAKE16-NEXT: s_movk_i32 s0, 0xbb8387; GFX1250-SDG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)388; GFX1250-SDG-FAKE16-NEXT: v_bitop3_b16 v0, s0, 0x7d0, v0 bitop3:0x15389; GFX1250-SDG-FAKE16-NEXT: ; return to shader part epilog390;391; GFX1250-GISEL-TRUE16-LABEL: bitop3_b16_iii:392; GFX1250-GISEL-TRUE16: ; %bb.0:393; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1394; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x7d0395; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0x3e8396; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)397; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, 0xbb8, v0.l, v0.h bitop3:0x15398; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog399;400; GFX1250-GISEL-FAKE16-LABEL: bitop3_b16_iii:401; GFX1250-GISEL-FAKE16: ; %bb.0:402; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1403; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, 0x7d0404; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0x3e8405; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)406; GFX1250-GISEL-FAKE16-NEXT: v_bitop3_b16 v0, 0xbb8, v0, v1 bitop3:0x15407; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog408 %ret = call i16 @llvm.amdgcn.bitop3.i16(i16 3000, i16 2000, i16 1000, i32 21)409 %ret_cast = bitcast i16 %ret to half410 ret half %ret_cast411}412;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:413; GCN: {{.*}}414