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1;RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck %s -check-prefix=CHECK2 3;CHECK-LABEL: {{^}}raw_buffer_store_format_immoffs_x3:4;CHECK-NOT: s_waitcnt5;CHECK: buffer_store_format_xyz v[0:2], off, s[0:3], 0 offset:426define amdgpu_ps void @raw_buffer_store_format_immoffs_x3(<4 x i32> inreg, <3 x float>) {7main_body:8 call void @llvm.amdgcn.raw.buffer.store.format.v3f32(<3 x float> %1, <4 x i32> %0, i32 42, i32 0, i32 0)9 ret void10}11 12;CHECK-LABEL: {{^}}raw_buffer_store_immoffs_x3:13;CHECK-NOT: s_waitcnt14;CHECK: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 offset:4215define amdgpu_ps void @raw_buffer_store_immoffs_x3(<4 x i32> inreg, <3 x float>) {16main_body:17 call void @llvm.amdgcn.raw.buffer.store.v3f32(<3 x float> %1, <4 x i32> %0, i32 42, i32 0, i32 0)18 ret void19}20 21;CHECK-LABEL: {{^}}struct_buffer_store_immoffs_x3:22;CHECK-NOT: s_waitcnt23;CHECK: buffer_store_dwordx3 v[0:2], {{v[0-9]+}}, s[0:3], 0 idxen offset:4224define amdgpu_ps void @struct_buffer_store_immoffs_x3(<4 x i32> inreg, <3 x float>) {25main_body:26 call void @llvm.amdgcn.struct.buffer.store.v3f32(<3 x float> %1, <4 x i32> %0, i32 0, i32 42, i32 0, i32 0)27 ret void28}29 30;CHECK-LABEL: {{^}}raw_ptr_buffer_store_format_immoffs_x3:31;CHECK-NOT: s_waitcnt32;CHECK: buffer_store_format_xyz v[0:2], off, s[0:3], 0 offset:4233define amdgpu_ps void @raw_ptr_buffer_store_format_immoffs_x3(ptr addrspace(8) inreg, <3 x float>) {34main_body:35 call void @llvm.amdgcn.raw.ptr.buffer.store.format.v3f32(<3 x float> %1, ptr addrspace(8) %0, i32 42, i32 0, i32 0)36 ret void37}38 39;CHECK-LABEL: {{^}}raw_ptr_buffer_store_immoffs_x3:40;CHECK-NOT: s_waitcnt41;CHECK: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 offset:4242define amdgpu_ps void @raw_ptr_buffer_store_immoffs_x3(ptr addrspace(8) inreg, <3 x float>) {43main_body:44 call void @llvm.amdgcn.raw.ptr.buffer.store.v3f32(<3 x float> %1, ptr addrspace(8) %0, i32 42, i32 0, i32 0)45 ret void46}47 48;CHECK-LABEL: {{^}}struct_ptr_buffer_store_immoffs_x3:49;CHECK-NOT: s_waitcnt50;CHECK: buffer_store_dwordx3 v[0:2], {{v[0-9]+}}, s[0:3], 0 idxen offset:4251define amdgpu_ps void @struct_ptr_buffer_store_immoffs_x3(ptr addrspace(8) inreg, <3 x float>) {52main_body:53 call void @llvm.amdgcn.struct.ptr.buffer.store.v3f32(<3 x float> %1, ptr addrspace(8) %0, i32 0, i32 42, i32 0, i32 0)54 ret void55}56 57declare void @llvm.amdgcn.raw.buffer.store.format.v3f32(<3 x float>, <4 x i32>, i32, i32, i32) #058declare void @llvm.amdgcn.raw.buffer.store.v3f32(<3 x float>, <4 x i32>, i32, i32, i32) #059declare void @llvm.amdgcn.struct.buffer.store.format.v3f32(<3 x float>, <4 x i32>, i32, i32, i32, i32) #060declare void @llvm.amdgcn.struct.buffer.store.v3f32(<3 x float>, <4 x i32>, i32, i32, i32, i32) #061declare void @llvm.amdgcn.raw.ptr.buffer.store.format.v3f32(<3 x float>, ptr addrspace(8), i32, i32, i32) #062declare void @llvm.amdgcn.raw.ptr.buffer.store.v3f32(<3 x float>, ptr addrspace(8), i32, i32, i32) #063declare void @llvm.amdgcn.struct.ptr.buffer.store.format.v3f32(<3 x float>, ptr addrspace(8), i32, i32, i32, i32) #064declare void @llvm.amdgcn.struct.ptr.buffer.store.v3f32(<3 x float>, ptr addrspace(8), i32, i32, i32, i32) #065