809 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=SI %s3 4declare i1 @llvm.amdgcn.class.f32(float, i32) #15declare i1 @llvm.amdgcn.class.f64(double, i32) #16declare i32 @llvm.amdgcn.workitem.id.x() #17declare float @llvm.fabs.f32(float) #18declare double @llvm.fabs.f64(double) #19 10define amdgpu_kernel void @test_class_f32(ptr addrspace(1) %out, [8 x i32], float %a, [8 x i32], i32 %b) #0 {11; SI-LABEL: test_class_f32:12; SI: ; %bb.0:13; SI-NEXT: s_load_dword s6, s[4:5], 0x1c14; SI-NEXT: s_load_dword s7, s[4:5], 0x1315; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x916; SI-NEXT: s_mov_b32 s3, 0xf00017; SI-NEXT: s_mov_b32 s2, -118; SI-NEXT: s_waitcnt lgkmcnt(0)19; SI-NEXT: v_mov_b32_e32 v0, s620; SI-NEXT: v_cmp_class_f32_e32 vcc, s7, v021; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc22; SI-NEXT: buffer_store_dword v0, off, s[0:3], 023; SI-NEXT: s_endpgm24 %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 %b) #125 %sext = sext i1 %result to i3226 store i32 %sext, ptr addrspace(1) %out, align 427 ret void28}29 30define amdgpu_kernel void @test_class_fabs_f32(ptr addrspace(1) %out, [8 x i32], float %a, [8 x i32], i32 %b) #0 {31; SI-LABEL: test_class_fabs_f32:32; SI: ; %bb.0:33; SI-NEXT: s_load_dword s6, s[4:5], 0x1c34; SI-NEXT: s_load_dword s7, s[4:5], 0x1335; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x936; SI-NEXT: s_mov_b32 s3, 0xf00037; SI-NEXT: s_mov_b32 s2, -138; SI-NEXT: s_waitcnt lgkmcnt(0)39; SI-NEXT: v_mov_b32_e32 v0, s640; SI-NEXT: v_cmp_class_f32_e64 s[4:5], |s7|, v041; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]42; SI-NEXT: buffer_store_dword v0, off, s[0:3], 043; SI-NEXT: s_endpgm44 %a.fabs = call float @llvm.fabs.f32(float %a) #145 %result = call i1 @llvm.amdgcn.class.f32(float %a.fabs, i32 %b) #146 %sext = sext i1 %result to i3247 store i32 %sext, ptr addrspace(1) %out, align 448 ret void49}50 51define amdgpu_kernel void @test_class_fneg_f32(ptr addrspace(1) %out, [8 x i32], float %a, [8 x i32], i32 %b) #0 {52; SI-LABEL: test_class_fneg_f32:53; SI: ; %bb.0:54; SI-NEXT: s_load_dword s6, s[4:5], 0x1c55; SI-NEXT: s_load_dword s7, s[4:5], 0x1356; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x957; SI-NEXT: s_mov_b32 s3, 0xf00058; SI-NEXT: s_mov_b32 s2, -159; SI-NEXT: s_waitcnt lgkmcnt(0)60; SI-NEXT: v_mov_b32_e32 v0, s661; SI-NEXT: v_cmp_class_f32_e64 s[4:5], -s7, v062; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]63; SI-NEXT: buffer_store_dword v0, off, s[0:3], 064; SI-NEXT: s_endpgm65 %a.fneg = fsub float -0.0, %a66 %result = call i1 @llvm.amdgcn.class.f32(float %a.fneg, i32 %b) #167 %sext = sext i1 %result to i3268 store i32 %sext, ptr addrspace(1) %out, align 469 ret void70}71 72define amdgpu_kernel void @test_class_fneg_fabs_f32(ptr addrspace(1) %out, [8 x i32], float %a, [8 x i32], i32 %b) #0 {73; SI-LABEL: test_class_fneg_fabs_f32:74; SI: ; %bb.0:75; SI-NEXT: s_load_dword s6, s[4:5], 0x1c76; SI-NEXT: s_load_dword s7, s[4:5], 0x1377; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x978; SI-NEXT: s_mov_b32 s3, 0xf00079; SI-NEXT: s_mov_b32 s2, -180; SI-NEXT: s_waitcnt lgkmcnt(0)81; SI-NEXT: v_mov_b32_e32 v0, s682; SI-NEXT: v_cmp_class_f32_e64 s[4:5], -|s7|, v083; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]84; SI-NEXT: buffer_store_dword v0, off, s[0:3], 085; SI-NEXT: s_endpgm86 %a.fabs = call float @llvm.fabs.f32(float %a) #187 %a.fneg.fabs = fsub float -0.0, %a.fabs88 %result = call i1 @llvm.amdgcn.class.f32(float %a.fneg.fabs, i32 %b) #189 %sext = sext i1 %result to i3290 store i32 %sext, ptr addrspace(1) %out, align 491 ret void92}93 94define amdgpu_kernel void @test_class_1_f32(ptr addrspace(1) %out, float %a) #0 {95; SI-LABEL: test_class_1_f32:96; SI: ; %bb.0:97; SI-NEXT: s_load_dword s6, s[4:5], 0xb98; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x999; SI-NEXT: s_mov_b32 s3, 0xf000100; SI-NEXT: s_mov_b32 s2, -1101; SI-NEXT: s_waitcnt lgkmcnt(0)102; SI-NEXT: v_cmp_class_f32_e64 s[4:5], s6, 1103; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]104; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0105; SI-NEXT: s_endpgm106 %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 1) #1107 %sext = sext i1 %result to i32108 store i32 %sext, ptr addrspace(1) %out, align 4109 ret void110}111 112define amdgpu_kernel void @test_class_64_f32(ptr addrspace(1) %out, float %a) #0 {113; SI-LABEL: test_class_64_f32:114; SI: ; %bb.0:115; SI-NEXT: s_load_dword s6, s[4:5], 0xb116; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9117; SI-NEXT: s_mov_b32 s3, 0xf000118; SI-NEXT: s_mov_b32 s2, -1119; SI-NEXT: s_waitcnt lgkmcnt(0)120; SI-NEXT: v_cmp_class_f32_e64 s[4:5], s6, 64121; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]122; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0123; SI-NEXT: s_endpgm124 %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 64) #1125 %sext = sext i1 %result to i32126 store i32 %sext, ptr addrspace(1) %out, align 4127 ret void128}129 130; Set all 10 bits of mask131define amdgpu_kernel void @test_class_full_mask_f32(ptr addrspace(1) %out, float %a) #0 {132; SI-LABEL: test_class_full_mask_f32:133; SI: ; %bb.0:134; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9135; SI-NEXT: s_load_dword s4, s[4:5], 0xb136; SI-NEXT: s_mov_b32 s3, 0xf000137; SI-NEXT: s_mov_b32 s2, -1138; SI-NEXT: v_mov_b32_e32 v0, 0x3ff139; SI-NEXT: s_waitcnt lgkmcnt(0)140; SI-NEXT: v_cmp_class_f32_e32 vcc, s4, v0141; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc142; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0143; SI-NEXT: s_endpgm144 %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 1023) #1145 %sext = sext i1 %result to i32146 store i32 %sext, ptr addrspace(1) %out, align 4147 ret void148}149 150define amdgpu_kernel void @test_class_9bit_mask_f32(ptr addrspace(1) %out, float %a) #0 {151; SI-LABEL: test_class_9bit_mask_f32:152; SI: ; %bb.0:153; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9154; SI-NEXT: s_load_dword s4, s[4:5], 0xb155; SI-NEXT: s_mov_b32 s3, 0xf000156; SI-NEXT: s_mov_b32 s2, -1157; SI-NEXT: v_mov_b32_e32 v0, 0x1ff158; SI-NEXT: s_waitcnt lgkmcnt(0)159; SI-NEXT: v_cmp_class_f32_e32 vcc, s4, v0160; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc161; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0162; SI-NEXT: s_endpgm163 %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 511) #1164 %sext = sext i1 %result to i32165 store i32 %sext, ptr addrspace(1) %out, align 4166 ret void167}168 169define amdgpu_kernel void @v_test_class_full_mask_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {170; SI-LABEL: v_test_class_full_mask_f32:171; SI: ; %bb.0:172; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9173; SI-NEXT: s_mov_b32 s7, 0xf000174; SI-NEXT: s_mov_b32 s6, 0175; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0176; SI-NEXT: v_mov_b32_e32 v1, 0177; SI-NEXT: s_waitcnt lgkmcnt(0)178; SI-NEXT: s_mov_b64 s[4:5], s[2:3]179; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64180; SI-NEXT: s_movk_i32 s4, 0x1ff181; SI-NEXT: s_mov_b64 s[2:3], s[6:7]182; SI-NEXT: s_waitcnt vmcnt(0)183; SI-NEXT: v_cmp_class_f32_e64 s[4:5], v2, s4184; SI-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[4:5]185; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64186; SI-NEXT: s_endpgm187 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1188 %gep.in = getelementptr float, ptr addrspace(1) %in, i32 %tid189 %gep.out = getelementptr i32, ptr addrspace(1) %out, i32 %tid190 %a = load float, ptr addrspace(1) %gep.in191 192 %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 511) #1193 %sext = sext i1 %result to i32194 store i32 %sext, ptr addrspace(1) %gep.out, align 4195 ret void196}197 198define amdgpu_kernel void @test_class_inline_imm_constant_dynamic_mask_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {199; SI-LABEL: test_class_inline_imm_constant_dynamic_mask_f32:200; SI: ; %bb.0:201; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9202; SI-NEXT: s_mov_b32 s7, 0xf000203; SI-NEXT: s_mov_b32 s6, 0204; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0205; SI-NEXT: v_mov_b32_e32 v1, 0206; SI-NEXT: s_waitcnt lgkmcnt(0)207; SI-NEXT: s_mov_b64 s[4:5], s[2:3]208; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64209; SI-NEXT: s_mov_b64 s[2:3], s[6:7]210; SI-NEXT: s_waitcnt vmcnt(0)211; SI-NEXT: v_cmp_class_f32_e32 vcc, 1.0, v2212; SI-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc213; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64214; SI-NEXT: s_endpgm215 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1216 %gep.in = getelementptr i32, ptr addrspace(1) %in, i32 %tid217 %gep.out = getelementptr i32, ptr addrspace(1) %out, i32 %tid218 %b = load i32, ptr addrspace(1) %gep.in219 220 %result = call i1 @llvm.amdgcn.class.f32(float 1.0, i32 %b) #1221 %sext = sext i1 %result to i32222 store i32 %sext, ptr addrspace(1) %gep.out, align 4223 ret void224}225 226; FIXME: Why isn't this using a literal constant operand?227define amdgpu_kernel void @test_class_lit_constant_dynamic_mask_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {228; SI-LABEL: test_class_lit_constant_dynamic_mask_f32:229; SI: ; %bb.0:230; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9231; SI-NEXT: s_mov_b32 s7, 0xf000232; SI-NEXT: s_mov_b32 s6, 0233; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0234; SI-NEXT: v_mov_b32_e32 v1, 0235; SI-NEXT: s_waitcnt lgkmcnt(0)236; SI-NEXT: s_mov_b64 s[4:5], s[2:3]237; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64238; SI-NEXT: s_mov_b32 s4, 0x44800000239; SI-NEXT: s_mov_b64 s[2:3], s[6:7]240; SI-NEXT: s_waitcnt vmcnt(0)241; SI-NEXT: v_cmp_class_f32_e32 vcc, s4, v2242; SI-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc243; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64244; SI-NEXT: s_endpgm245 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1246 %gep.in = getelementptr i32, ptr addrspace(1) %in, i32 %tid247 %gep.out = getelementptr i32, ptr addrspace(1) %out, i32 %tid248 %b = load i32, ptr addrspace(1) %gep.in249 250 %result = call i1 @llvm.amdgcn.class.f32(float 1024.0, i32 %b) #1251 %sext = sext i1 %result to i32252 store i32 %sext, ptr addrspace(1) %gep.out, align 4253 ret void254}255 256define amdgpu_kernel void @test_class_f64(ptr addrspace(1) %out, [8 x i32], double %a, [8 x i32], i32 %b) #0 {257; SI-LABEL: test_class_f64:258; SI: ; %bb.0:259; SI-NEXT: s_load_dword s8, s[4:5], 0x1d260; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x13261; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9262; SI-NEXT: s_mov_b32 s3, 0xf000263; SI-NEXT: s_mov_b32 s2, -1264; SI-NEXT: s_waitcnt lgkmcnt(0)265; SI-NEXT: v_mov_b32_e32 v0, s8266; SI-NEXT: v_cmp_class_f64_e32 vcc, s[6:7], v0267; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc268; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0269; SI-NEXT: s_endpgm270 %result = call i1 @llvm.amdgcn.class.f64(double %a, i32 %b) #1271 %sext = sext i1 %result to i32272 store i32 %sext, ptr addrspace(1) %out, align 4273 ret void274}275 276define amdgpu_kernel void @test_class_fabs_f64(ptr addrspace(1) %out, [8 x i32], double %a, [8 x i32], i32 %b) #0 {277; SI-LABEL: test_class_fabs_f64:278; SI: ; %bb.0:279; SI-NEXT: s_load_dword s8, s[4:5], 0x1d280; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x13281; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9282; SI-NEXT: s_mov_b32 s3, 0xf000283; SI-NEXT: s_mov_b32 s2, -1284; SI-NEXT: s_waitcnt lgkmcnt(0)285; SI-NEXT: v_mov_b32_e32 v0, s8286; SI-NEXT: v_cmp_class_f64_e64 s[4:5], |s[6:7]|, v0287; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]288; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0289; SI-NEXT: s_endpgm290 %a.fabs = call double @llvm.fabs.f64(double %a) #1291 %result = call i1 @llvm.amdgcn.class.f64(double %a.fabs, i32 %b) #1292 %sext = sext i1 %result to i32293 store i32 %sext, ptr addrspace(1) %out, align 4294 ret void295}296 297define amdgpu_kernel void @test_class_fneg_f64(ptr addrspace(1) %out, [8 x i32], double %a, [8 x i32], i32 %b) #0 {298; SI-LABEL: test_class_fneg_f64:299; SI: ; %bb.0:300; SI-NEXT: s_load_dword s8, s[4:5], 0x1d301; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x13302; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9303; SI-NEXT: s_mov_b32 s3, 0xf000304; SI-NEXT: s_mov_b32 s2, -1305; SI-NEXT: s_waitcnt lgkmcnt(0)306; SI-NEXT: v_mov_b32_e32 v0, s8307; SI-NEXT: v_cmp_class_f64_e64 s[4:5], -s[6:7], v0308; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]309; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0310; SI-NEXT: s_endpgm311 %a.fneg = fsub double -0.0, %a312 %result = call i1 @llvm.amdgcn.class.f64(double %a.fneg, i32 %b) #1313 %sext = sext i1 %result to i32314 store i32 %sext, ptr addrspace(1) %out, align 4315 ret void316}317 318define amdgpu_kernel void @test_class_fneg_fabs_f64(ptr addrspace(1) %out, [8 x i32], double %a, [8 x i32], i32 %b) #0 {319; SI-LABEL: test_class_fneg_fabs_f64:320; SI: ; %bb.0:321; SI-NEXT: s_load_dword s8, s[4:5], 0x1d322; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x13323; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9324; SI-NEXT: s_mov_b32 s3, 0xf000325; SI-NEXT: s_mov_b32 s2, -1326; SI-NEXT: s_waitcnt lgkmcnt(0)327; SI-NEXT: v_mov_b32_e32 v0, s8328; SI-NEXT: v_cmp_class_f64_e64 s[4:5], -|s[6:7]|, v0329; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]330; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0331; SI-NEXT: s_endpgm332 %a.fabs = call double @llvm.fabs.f64(double %a) #1333 %a.fneg.fabs = fsub double -0.0, %a.fabs334 %result = call i1 @llvm.amdgcn.class.f64(double %a.fneg.fabs, i32 %b) #1335 %sext = sext i1 %result to i32336 store i32 %sext, ptr addrspace(1) %out, align 4337 ret void338}339 340define amdgpu_kernel void @test_class_1_f64(ptr addrspace(1) %out, double %a) #0 {341; SI-LABEL: test_class_1_f64:342; SI: ; %bb.0:343; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9344; SI-NEXT: s_mov_b32 s7, 0xf000345; SI-NEXT: s_mov_b32 s6, -1346; SI-NEXT: s_waitcnt lgkmcnt(0)347; SI-NEXT: s_mov_b32 s4, s0348; SI-NEXT: s_mov_b32 s5, s1349; SI-NEXT: v_cmp_class_f64_e64 s[0:1], s[2:3], 1350; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]351; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0352; SI-NEXT: s_endpgm353 %result = call i1 @llvm.amdgcn.class.f64(double %a, i32 1) #1354 %sext = sext i1 %result to i32355 store i32 %sext, ptr addrspace(1) %out, align 4356 ret void357}358 359define amdgpu_kernel void @test_class_64_f64(ptr addrspace(1) %out, double %a) #0 {360; SI-LABEL: test_class_64_f64:361; SI: ; %bb.0:362; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9363; SI-NEXT: s_mov_b32 s7, 0xf000364; SI-NEXT: s_mov_b32 s6, -1365; SI-NEXT: s_waitcnt lgkmcnt(0)366; SI-NEXT: s_mov_b32 s4, s0367; SI-NEXT: s_mov_b32 s5, s1368; SI-NEXT: v_cmp_class_f64_e64 s[0:1], s[2:3], 64369; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]370; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0371; SI-NEXT: s_endpgm372 %result = call i1 @llvm.amdgcn.class.f64(double %a, i32 64) #1373 %sext = sext i1 %result to i32374 store i32 %sext, ptr addrspace(1) %out, align 4375 ret void376}377 378; Set all 9 bits of mask379define amdgpu_kernel void @test_class_full_mask_f64(ptr addrspace(1) %out, [8 x i32], double %a) #0 {380; SI-LABEL: test_class_full_mask_f64:381; SI: ; %bb.0:382; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9383; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x13384; SI-NEXT: s_mov_b32 s3, 0xf000385; SI-NEXT: s_mov_b32 s2, -1386; SI-NEXT: v_mov_b32_e32 v0, 0x1ff387; SI-NEXT: s_waitcnt lgkmcnt(0)388; SI-NEXT: v_cmp_class_f64_e32 vcc, s[4:5], v0389; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc390; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0391; SI-NEXT: s_endpgm392 %result = call i1 @llvm.amdgcn.class.f64(double %a, i32 511) #1393 %sext = sext i1 %result to i32394 store i32 %sext, ptr addrspace(1) %out, align 4395 ret void396}397 398define amdgpu_kernel void @v_test_class_full_mask_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {399; SI-LABEL: v_test_class_full_mask_f64:400; SI: ; %bb.0:401; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9402; SI-NEXT: s_mov_b32 s7, 0xf000403; SI-NEXT: s_mov_b32 s6, -1404; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0405; SI-NEXT: s_waitcnt lgkmcnt(0)406; SI-NEXT: s_mov_b32 s4, s2407; SI-NEXT: s_mov_b32 s5, s3408; SI-NEXT: buffer_load_dwordx2 v[2:3], off, s[4:7], 0409; SI-NEXT: v_mov_b32_e32 v1, 0410; SI-NEXT: s_movk_i32 s4, 0x1ff411; SI-NEXT: s_mov_b32 s2, 0412; SI-NEXT: s_mov_b32 s3, s7413; SI-NEXT: s_waitcnt vmcnt(0)414; SI-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], s4415; SI-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[4:5]416; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64417; SI-NEXT: s_endpgm418 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1419 %gep.in = getelementptr double, ptr addrspace(1) %in, i32 %tid420 %gep.out = getelementptr i32, ptr addrspace(1) %out, i32 %tid421 %a = load double, ptr addrspace(1) %in422 423 %result = call i1 @llvm.amdgcn.class.f64(double %a, i32 511) #1424 %sext = sext i1 %result to i32425 store i32 %sext, ptr addrspace(1) %gep.out, align 4426 ret void427}428 429define amdgpu_kernel void @test_class_inline_imm_constant_dynamic_mask_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {430; SI-LABEL: test_class_inline_imm_constant_dynamic_mask_f64:431; SI: ; %bb.0:432; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9433; SI-NEXT: s_mov_b32 s7, 0xf000434; SI-NEXT: s_mov_b32 s6, 0435; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0436; SI-NEXT: v_mov_b32_e32 v1, 0437; SI-NEXT: s_waitcnt lgkmcnt(0)438; SI-NEXT: s_mov_b64 s[4:5], s[2:3]439; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64440; SI-NEXT: s_mov_b64 s[2:3], s[6:7]441; SI-NEXT: s_waitcnt vmcnt(0)442; SI-NEXT: v_cmp_class_f64_e32 vcc, 1.0, v2443; SI-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc444; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64445; SI-NEXT: s_endpgm446 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1447 %gep.in = getelementptr i32, ptr addrspace(1) %in, i32 %tid448 %gep.out = getelementptr i32, ptr addrspace(1) %out, i32 %tid449 %b = load i32, ptr addrspace(1) %gep.in450 451 %result = call i1 @llvm.amdgcn.class.f64(double 1.0, i32 %b) #1452 %sext = sext i1 %result to i32453 store i32 %sext, ptr addrspace(1) %gep.out, align 4454 ret void455}456 457define amdgpu_kernel void @test_class_lit_constant_dynamic_mask_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {458; SI-LABEL: test_class_lit_constant_dynamic_mask_f64:459; SI: ; %bb.0:460; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9461; SI-NEXT: s_mov_b32 s7, 0xf000462; SI-NEXT: s_mov_b32 s6, 0463; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0464; SI-NEXT: v_mov_b32_e32 v1, 0465; SI-NEXT: s_waitcnt lgkmcnt(0)466; SI-NEXT: s_mov_b64 s[4:5], s[2:3]467; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64468; SI-NEXT: s_mov_b32 s4, 0469; SI-NEXT: s_mov_b32 s5, 0x40900000470; SI-NEXT: s_mov_b64 s[2:3], s[6:7]471; SI-NEXT: s_waitcnt vmcnt(0)472; SI-NEXT: v_cmp_class_f64_e32 vcc, s[4:5], v2473; SI-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc474; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64475; SI-NEXT: s_endpgm476 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1477 %gep.in = getelementptr i32, ptr addrspace(1) %in, i32 %tid478 %gep.out = getelementptr i32, ptr addrspace(1) %out, i32 %tid479 %b = load i32, ptr addrspace(1) %gep.in480 481 %result = call i1 @llvm.amdgcn.class.f64(double 1024.0, i32 %b) #1482 %sext = sext i1 %result to i32483 store i32 %sext, ptr addrspace(1) %gep.out, align 4484 ret void485}486 487define amdgpu_kernel void @test_fold_or_class_f32_0(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {488; SI-LABEL: test_fold_or_class_f32_0:489; SI: ; %bb.0:490; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9491; SI-NEXT: s_mov_b32 s7, 0xf000492; SI-NEXT: s_mov_b32 s10, 0493; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0494; SI-NEXT: v_mov_b32_e32 v1, 0495; SI-NEXT: s_mov_b32 s11, s7496; SI-NEXT: s_waitcnt lgkmcnt(0)497; SI-NEXT: s_mov_b64 s[8:9], s[2:3]498; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64499; SI-NEXT: s_mov_b32 s6, -1500; SI-NEXT: s_mov_b32 s4, s0501; SI-NEXT: s_mov_b32 s5, s1502; SI-NEXT: s_waitcnt vmcnt(0)503; SI-NEXT: v_cmp_class_f32_e64 s[0:1], v0, 3504; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]505; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0506; SI-NEXT: s_endpgm507 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1508 %gep.in = getelementptr float, ptr addrspace(1) %in, i32 %tid509 %gep.out = getelementptr i32, ptr addrspace(1) %out, i32 %tid510 %a = load float, ptr addrspace(1) %gep.in511 512 %class0 = call i1 @llvm.amdgcn.class.f32(float %a, i32 1) #1513 %class1 = call i1 @llvm.amdgcn.class.f32(float %a, i32 3) #1514 %or = or i1 %class0, %class1515 516 %sext = sext i1 %or to i32517 store i32 %sext, ptr addrspace(1) %out, align 4518 ret void519}520 521define amdgpu_kernel void @test_fold_or3_class_f32_0(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {522; SI-LABEL: test_fold_or3_class_f32_0:523; SI: ; %bb.0:524; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9525; SI-NEXT: s_mov_b32 s7, 0xf000526; SI-NEXT: s_mov_b32 s10, 0527; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0528; SI-NEXT: v_mov_b32_e32 v1, 0529; SI-NEXT: s_mov_b32 s11, s7530; SI-NEXT: s_waitcnt lgkmcnt(0)531; SI-NEXT: s_mov_b64 s[8:9], s[2:3]532; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64533; SI-NEXT: s_mov_b32 s6, -1534; SI-NEXT: s_mov_b32 s4, s0535; SI-NEXT: s_mov_b32 s5, s1536; SI-NEXT: s_waitcnt vmcnt(0)537; SI-NEXT: v_cmp_class_f32_e64 s[0:1], v0, 7538; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]539; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0540; SI-NEXT: s_endpgm541 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1542 %gep.in = getelementptr float, ptr addrspace(1) %in, i32 %tid543 %gep.out = getelementptr i32, ptr addrspace(1) %out, i32 %tid544 %a = load float, ptr addrspace(1) %gep.in545 546 %class0 = call i1 @llvm.amdgcn.class.f32(float %a, i32 1) #1547 %class1 = call i1 @llvm.amdgcn.class.f32(float %a, i32 2) #1548 %class2 = call i1 @llvm.amdgcn.class.f32(float %a, i32 4) #1549 %or.0 = or i1 %class0, %class1550 %or.1 = or i1 %or.0, %class2551 552 %sext = sext i1 %or.1 to i32553 store i32 %sext, ptr addrspace(1) %out, align 4554 ret void555}556 557define amdgpu_kernel void @test_fold_or_all_tests_class_f32_0(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {558; SI-LABEL: test_fold_or_all_tests_class_f32_0:559; SI: ; %bb.0:560; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9561; SI-NEXT: s_mov_b32 s7, 0xf000562; SI-NEXT: s_mov_b32 s10, 0563; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0564; SI-NEXT: v_mov_b32_e32 v1, 0565; SI-NEXT: s_mov_b32 s11, s7566; SI-NEXT: s_waitcnt lgkmcnt(0)567; SI-NEXT: s_mov_b64 s[8:9], s[2:3]568; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64569; SI-NEXT: s_mov_b32 s6, -1570; SI-NEXT: s_movk_i32 s2, 0x3ff571; SI-NEXT: s_mov_b32 s4, s0572; SI-NEXT: s_mov_b32 s5, s1573; SI-NEXT: s_waitcnt vmcnt(0)574; SI-NEXT: v_cmp_class_f32_e64 s[0:1], v0, s2575; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]576; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0577; SI-NEXT: s_endpgm578 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1579 %gep.in = getelementptr float, ptr addrspace(1) %in, i32 %tid580 %gep.out = getelementptr i32, ptr addrspace(1) %out, i32 %tid581 %a = load float, ptr addrspace(1) %gep.in582 583 %class0 = call i1 @llvm.amdgcn.class.f32(float %a, i32 1) #1584 %class1 = call i1 @llvm.amdgcn.class.f32(float %a, i32 2) #1585 %class2 = call i1 @llvm.amdgcn.class.f32(float %a, i32 4) #1586 %class3 = call i1 @llvm.amdgcn.class.f32(float %a, i32 8) #1587 %class4 = call i1 @llvm.amdgcn.class.f32(float %a, i32 16) #1588 %class5 = call i1 @llvm.amdgcn.class.f32(float %a, i32 32) #1589 %class6 = call i1 @llvm.amdgcn.class.f32(float %a, i32 64) #1590 %class7 = call i1 @llvm.amdgcn.class.f32(float %a, i32 128) #1591 %class8 = call i1 @llvm.amdgcn.class.f32(float %a, i32 256) #1592 %class9 = call i1 @llvm.amdgcn.class.f32(float %a, i32 512) #1593 %or.0 = or i1 %class0, %class1594 %or.1 = or i1 %or.0, %class2595 %or.2 = or i1 %or.1, %class3596 %or.3 = or i1 %or.2, %class4597 %or.4 = or i1 %or.3, %class5598 %or.5 = or i1 %or.4, %class6599 %or.6 = or i1 %or.5, %class7600 %or.7 = or i1 %or.6, %class8601 %or.8 = or i1 %or.7, %class9602 %sext = sext i1 %or.8 to i32603 store i32 %sext, ptr addrspace(1) %out, align 4604 ret void605}606 607define amdgpu_kernel void @test_fold_or_class_f32_1(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {608; SI-LABEL: test_fold_or_class_f32_1:609; SI: ; %bb.0:610; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9611; SI-NEXT: s_mov_b32 s7, 0xf000612; SI-NEXT: s_mov_b32 s10, 0613; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0614; SI-NEXT: v_mov_b32_e32 v1, 0615; SI-NEXT: s_mov_b32 s11, s7616; SI-NEXT: s_waitcnt lgkmcnt(0)617; SI-NEXT: s_mov_b64 s[8:9], s[2:3]618; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64619; SI-NEXT: s_mov_b32 s6, -1620; SI-NEXT: s_mov_b32 s4, s0621; SI-NEXT: s_mov_b32 s5, s1622; SI-NEXT: s_waitcnt vmcnt(0)623; SI-NEXT: v_cmp_class_f32_e64 s[0:1], v0, 12624; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]625; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0626; SI-NEXT: s_endpgm627 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1628 %gep.in = getelementptr float, ptr addrspace(1) %in, i32 %tid629 %gep.out = getelementptr i32, ptr addrspace(1) %out, i32 %tid630 %a = load float, ptr addrspace(1) %gep.in631 632 %class0 = call i1 @llvm.amdgcn.class.f32(float %a, i32 4) #1633 %class1 = call i1 @llvm.amdgcn.class.f32(float %a, i32 8) #1634 %or = or i1 %class0, %class1635 636 %sext = sext i1 %or to i32637 store i32 %sext, ptr addrspace(1) %out, align 4638 ret void639}640 641define amdgpu_kernel void @test_fold_or_class_f32_2(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {642; SI-LABEL: test_fold_or_class_f32_2:643; SI: ; %bb.0:644; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9645; SI-NEXT: s_mov_b32 s7, 0xf000646; SI-NEXT: s_mov_b32 s10, 0647; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0648; SI-NEXT: v_mov_b32_e32 v1, 0649; SI-NEXT: s_mov_b32 s11, s7650; SI-NEXT: s_waitcnt lgkmcnt(0)651; SI-NEXT: s_mov_b64 s[8:9], s[2:3]652; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64653; SI-NEXT: s_mov_b32 s6, -1654; SI-NEXT: s_mov_b32 s4, s0655; SI-NEXT: s_mov_b32 s5, s1656; SI-NEXT: s_waitcnt vmcnt(0)657; SI-NEXT: v_cmp_class_f32_e64 s[0:1], v0, 7658; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]659; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0660; SI-NEXT: s_endpgm661 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1662 %gep.in = getelementptr float, ptr addrspace(1) %in, i32 %tid663 %gep.out = getelementptr i32, ptr addrspace(1) %out, i32 %tid664 %a = load float, ptr addrspace(1) %gep.in665 666 %class0 = call i1 @llvm.amdgcn.class.f32(float %a, i32 7) #1667 %class1 = call i1 @llvm.amdgcn.class.f32(float %a, i32 7) #1668 %or = or i1 %class0, %class1669 670 %sext = sext i1 %or to i32671 store i32 %sext, ptr addrspace(1) %out, align 4672 ret void673}674 675define amdgpu_kernel void @test_no_fold_or_class_f32_0(ptr addrspace(1) %out, ptr addrspace(1) %in, float %b) #0 {676; SI-LABEL: test_no_fold_or_class_f32_0:677; SI: ; %bb.0:678; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9679; SI-NEXT: s_load_dword s12, s[4:5], 0xd680; SI-NEXT: s_mov_b32 s7, 0xf000681; SI-NEXT: s_mov_b32 s10, 0682; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0683; SI-NEXT: v_mov_b32_e32 v1, 0684; SI-NEXT: s_mov_b32 s11, s7685; SI-NEXT: s_waitcnt lgkmcnt(0)686; SI-NEXT: s_mov_b64 s[8:9], s[2:3]687; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64688; SI-NEXT: s_mov_b32 s6, -1689; SI-NEXT: s_mov_b32 s4, s0690; SI-NEXT: s_mov_b32 s5, s1691; SI-NEXT: v_cmp_class_f32_e64 s[0:1], s12, 8692; SI-NEXT: s_waitcnt vmcnt(0)693; SI-NEXT: v_cmp_class_f32_e64 s[2:3], v0, 4694; SI-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]695; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]696; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0697; SI-NEXT: s_endpgm698 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1699 %gep.in = getelementptr float, ptr addrspace(1) %in, i32 %tid700 %gep.out = getelementptr i32, ptr addrspace(1) %out, i32 %tid701 %a = load float, ptr addrspace(1) %gep.in702 703 %class0 = call i1 @llvm.amdgcn.class.f32(float %a, i32 4) #1704 %class1 = call i1 @llvm.amdgcn.class.f32(float %b, i32 8) #1705 %or = or i1 %class0, %class1706 707 %sext = sext i1 %or to i32708 store i32 %sext, ptr addrspace(1) %out, align 4709 ret void710}711 712define amdgpu_kernel void @test_class_0_f32(ptr addrspace(1) %out, float %a) #0 {713; SI-LABEL: test_class_0_f32:714; SI: ; %bb.0:715; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9716; SI-NEXT: s_mov_b32 s3, 0xf000717; SI-NEXT: s_mov_b32 s2, -1718; SI-NEXT: v_mov_b32_e32 v0, 0719; SI-NEXT: s_waitcnt lgkmcnt(0)720; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0721; SI-NEXT: s_endpgm722 %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 0) #1723 %sext = sext i1 %result to i32724 store i32 %sext, ptr addrspace(1) %out, align 4725 ret void726}727 728define amdgpu_kernel void @test_class_0_f64(ptr addrspace(1) %out, double %a) #0 {729; SI-LABEL: test_class_0_f64:730; SI: ; %bb.0:731; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9732; SI-NEXT: s_waitcnt lgkmcnt(0)733; SI-NEXT: s_mov_b32 s3, 0xf000734; SI-NEXT: s_mov_b32 s2, -1735; SI-NEXT: v_mov_b32_e32 v0, 0736; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0737; SI-NEXT: s_endpgm738 %result = call i1 @llvm.amdgcn.class.f64(double %a, i32 0) #1739 %sext = sext i1 %result to i32740 store i32 %sext, ptr addrspace(1) %out, align 4741 ret void742}743 744define amdgpu_kernel void @test_class_undef_f32(ptr addrspace(1) %out, float %a, i32 %b) #0 {745; SI-LABEL: test_class_undef_f32:746; SI: ; %bb.0:747; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9748; SI-NEXT: s_mov_b32 s3, 0xf000749; SI-NEXT: s_mov_b32 s2, -1750; SI-NEXT: v_mov_b32_e32 v0, 0751; SI-NEXT: s_waitcnt lgkmcnt(0)752; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0753; SI-NEXT: s_endpgm754 %result = call i1 @llvm.amdgcn.class.f32(float poison, i32 %b) #1755 %sext = sext i1 %result to i32756 store i32 %sext, ptr addrspace(1) %out, align 4757 ret void758}759 760define i1 @test_fold_and_ord(float %a) {761; SI-LABEL: test_fold_and_ord:762; SI: ; %bb.0:763; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)764; SI-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 32765; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]766; SI-NEXT: s_setpc_b64 s[30:31]767 %class = call i1 @llvm.amdgcn.class.f32(float %a, i32 35) #1768 %ord = fcmp ord float %a, %a769 %and = and i1 %ord, %class770 ret i1 %and771}772 773define i1 @test_fold_and_unord(float %a) {774; SI-LABEL: test_fold_and_unord:775; SI: ; %bb.0:776; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)777; SI-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 3778; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]779; SI-NEXT: s_setpc_b64 s[30:31]780 %class = call i1 @llvm.amdgcn.class.f32(float %a, i32 35) #1781 %ord = fcmp uno float %a, %a782 %and = and i1 %ord, %class783 ret i1 %and784}785 786define i1 @test_fold_and_ord_multi_use(float %a) {787; SI-LABEL: test_fold_and_ord_multi_use:788; SI: ; %bb.0:789; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)790; SI-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 35791; SI-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]792; SI-NEXT: s_mov_b32 s7, 0xf000793; SI-NEXT: s_mov_b32 s6, -1794; SI-NEXT: v_cmp_o_f32_e32 vcc, v0, v0795; SI-NEXT: s_and_b64 s[4:5], vcc, s[4:5]796; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]797; SI-NEXT: buffer_store_byte v1, off, s[4:7], 0798; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)799; SI-NEXT: s_setpc_b64 s[30:31]800 %class = call i1 @llvm.amdgcn.class.f32(float %a, i32 35) #1801 store volatile i1 %class, ptr addrspace(1) poison802 %ord = fcmp ord float %a, %a803 %and = and i1 %ord, %class804 ret i1 %and805}806 807attributes #0 = { nounwind }808attributes #1 = { nounwind readnone }809