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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s3; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s4 5declare void @llvm.amdgcn.cluster.load.async.to.lds.b8(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr, i32 %offset, i32 %cpol, i32 %mask)6declare void @llvm.amdgcn.cluster.load.async.to.lds.b32(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr, i32 %offset, i32 %cpol, i32 %mask)7declare void @llvm.amdgcn.cluster.load.async.to.lds.b64(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr, i32 %offset, i32 %cpol, i32 %mask)8declare void @llvm.amdgcn.cluster.load.async.to.lds.b128(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr, i32 %offset, i32 %cpol, i32 %mask)9 10define amdgpu_ps void @cluster_load_async_to_lds_b8_vaddr(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr, i32 %mask) {11; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b8_vaddr:12; GFX1250-SDAG: ; %bb.0: ; %entry13; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 114; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]15; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v316; GFX1250-SDAG-NEXT: s_mov_b32 m0, s017; GFX1250-SDAG-NEXT: cluster_load_async_to_lds_b8 v2, v[0:1], off offset:16 th:TH_LOAD_NT18; GFX1250-SDAG-NEXT: s_endpgm19;20; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b8_vaddr:21; GFX1250-GISEL: ; %bb.0: ; %entry22; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 123; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v324; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3225; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)26; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo27; GFX1250-GISEL-NEXT: s_mov_b32 m0, s028; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b8 v2, v[0:1], off offset:16 th:TH_LOAD_NT29; GFX1250-GISEL-NEXT: s_endpgm30entry:31 %gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 432 call void @llvm.amdgcn.cluster.load.async.to.lds.b8(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 1, i32 %mask)33 ret void34}35 36define amdgpu_ps void @cluster_load_async_to_lds_b8_vaddr_imm_mask(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr) {37; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b8_vaddr_imm_mask:38; GFX1250-SDAG: ; %bb.0: ; %entry39; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 140; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]41; GFX1250-SDAG-NEXT: s_mov_b32 m0, 1542; GFX1250-SDAG-NEXT: cluster_load_async_to_lds_b8 v2, v[0:1], off offset:1643; GFX1250-SDAG-NEXT: s_endpgm44;45; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b8_vaddr_imm_mask:46; GFX1250-GISEL: ; %bb.0: ; %entry47; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 148; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3249; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)50; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo51; GFX1250-GISEL-NEXT: s_mov_b32 m0, 1552; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b8 v2, v[0:1], off offset:1653; GFX1250-GISEL-NEXT: s_endpgm54entry:55 %gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 456 call void @llvm.amdgcn.cluster.load.async.to.lds.b8(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 0, i32 15)57 ret void58}59 60define amdgpu_ps void @cluster_load_async_to_lds_b8_saddr(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask) {61; GFX1250-LABEL: cluster_load_async_to_lds_b8_saddr:62; GFX1250: ; %bb.0: ; %entry63; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 164; GFX1250-NEXT: v_mov_b32_e32 v1, 3265; GFX1250-NEXT: s_mov_b32 m0, s266; GFX1250-NEXT: cluster_load_async_to_lds_b8 v0, v1, s[0:1] offset:1667; GFX1250-NEXT: s_endpgm68entry:69 %gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 470 call void @llvm.amdgcn.cluster.load.async.to.lds.b8(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 0, i32 %mask)71 ret void72}73 74define amdgpu_ps void @cluster_load_async_to_lds_b32_vaddr(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr, i32 %mask) {75; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b32_vaddr:76; GFX1250-SDAG: ; %bb.0: ; %entry77; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 178; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]79; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v380; GFX1250-SDAG-NEXT: s_mov_b32 m0, s081; GFX1250-SDAG-NEXT: cluster_load_async_to_lds_b32 v2, v[0:1], off offset:16 th:TH_LOAD_HT scope:SCOPE_SE82; GFX1250-SDAG-NEXT: s_endpgm83;84; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b32_vaddr:85; GFX1250-GISEL: ; %bb.0: ; %entry86; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 187; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v388; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3289; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)90; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo91; GFX1250-GISEL-NEXT: s_mov_b32 m0, s092; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b32 v2, v[0:1], off offset:16 th:TH_LOAD_HT scope:SCOPE_SE93; GFX1250-GISEL-NEXT: s_endpgm94entry:95 %gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 496 call void @llvm.amdgcn.cluster.load.async.to.lds.b32(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 10, i32 %mask)97 ret void98}99 100define amdgpu_ps void @cluster_load_async_to_lds_b32_vaddr_imm_mask(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr) {101; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b32_vaddr_imm_mask:102; GFX1250-SDAG: ; %bb.0: ; %entry103; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1104; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]105; GFX1250-SDAG-NEXT: s_mov_b32 m0, 15106; GFX1250-SDAG-NEXT: cluster_load_async_to_lds_b32 v2, v[0:1], off offset:16107; GFX1250-SDAG-NEXT: s_endpgm108;109; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b32_vaddr_imm_mask:110; GFX1250-GISEL: ; %bb.0: ; %entry111; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1112; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32113; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)114; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo115; GFX1250-GISEL-NEXT: s_mov_b32 m0, 15116; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b32 v2, v[0:1], off offset:16117; GFX1250-GISEL-NEXT: s_endpgm118entry:119 %gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4120 call void @llvm.amdgcn.cluster.load.async.to.lds.b32(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 0, i32 15)121 ret void122}123 124define amdgpu_ps void @cluster_load_async_to_lds_b32_saddr( ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask) {125; GFX1250-LABEL: cluster_load_async_to_lds_b32_saddr:126; GFX1250: ; %bb.0: ; %entry127; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1128; GFX1250-NEXT: v_mov_b32_e32 v1, 32129; GFX1250-NEXT: s_mov_b32 m0, s2130; GFX1250-NEXT: cluster_load_async_to_lds_b32 v0, v1, s[0:1] offset:16131; GFX1250-NEXT: s_endpgm132entry:133 %gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4134 call void @llvm.amdgcn.cluster.load.async.to.lds.b32(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 0, i32 %mask)135 ret void136}137 138define amdgpu_ps void @cluster_load_async_to_lds_b64_vaddr(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr, i32 %mask) {139; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b64_vaddr:140; GFX1250-SDAG: ; %bb.0: ; %entry141; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1142; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]143; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v3144; GFX1250-SDAG-NEXT: s_mov_b32 m0, s0145; GFX1250-SDAG-NEXT: cluster_load_async_to_lds_b64 v2, v[0:1], off offset:16 th:TH_LOAD_NT_HT scope:SCOPE_DEV146; GFX1250-SDAG-NEXT: s_endpgm147;148; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b64_vaddr:149; GFX1250-GISEL: ; %bb.0: ; %entry150; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1151; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v3152; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32153; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)154; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo155; GFX1250-GISEL-NEXT: s_mov_b32 m0, s0156; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b64 v2, v[0:1], off offset:16 th:TH_LOAD_NT_HT scope:SCOPE_DEV157; GFX1250-GISEL-NEXT: s_endpgm158entry:159 %gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4160 call void @llvm.amdgcn.cluster.load.async.to.lds.b64(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 22, i32 %mask)161 ret void162}163 164define amdgpu_ps void @cluster_load_async_to_lds_b64_vaddr_imm_mask( ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr) {165; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b64_vaddr_imm_mask:166; GFX1250-SDAG: ; %bb.0: ; %entry167; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1168; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]169; GFX1250-SDAG-NEXT: s_movk_i32 m0, 0x7f170; GFX1250-SDAG-NEXT: cluster_load_async_to_lds_b64 v2, v[0:1], off offset:16171; GFX1250-SDAG-NEXT: s_endpgm172;173; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b64_vaddr_imm_mask:174; GFX1250-GISEL: ; %bb.0: ; %entry175; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1176; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32177; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)178; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo179; GFX1250-GISEL-NEXT: s_movk_i32 m0, 0x7f180; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b64 v2, v[0:1], off offset:16181; GFX1250-GISEL-NEXT: s_endpgm182entry:183 %gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4184 call void @llvm.amdgcn.cluster.load.async.to.lds.b64(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 0, i32 127)185 ret void186}187 188define amdgpu_ps void @cluster_load_async_to_lds_b64_saddr(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask) {189; GFX1250-LABEL: cluster_load_async_to_lds_b64_saddr:190; GFX1250: ; %bb.0: ; %entry191; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1192; GFX1250-NEXT: v_mov_b32_e32 v1, 32193; GFX1250-NEXT: s_mov_b32 m0, s2194; GFX1250-NEXT: cluster_load_async_to_lds_b64 v0, v1, s[0:1] offset:16195; GFX1250-NEXT: s_endpgm196entry:197 %gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4198 call void @llvm.amdgcn.cluster.load.async.to.lds.b64(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 0, i32 %mask)199 ret void200}201 202define amdgpu_ps void @cluster_load_async_to_lds_b128_vaddr(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr, i32 %mask) {203; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b128_vaddr:204; GFX1250-SDAG: ; %bb.0: ; %entry205; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1206; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]207; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v3208; GFX1250-SDAG-NEXT: s_mov_b32 m0, s0209; GFX1250-SDAG-NEXT: cluster_load_async_to_lds_b128 v2, v[0:1], off offset:16 th:TH_LOAD_BYPASS scope:SCOPE_SYS210; GFX1250-SDAG-NEXT: s_endpgm211;212; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b128_vaddr:213; GFX1250-GISEL: ; %bb.0: ; %entry214; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1215; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v3216; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32217; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)218; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo219; GFX1250-GISEL-NEXT: s_mov_b32 m0, s0220; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b128 v2, v[0:1], off offset:16 th:TH_LOAD_BYPASS scope:SCOPE_SYS221; GFX1250-GISEL-NEXT: s_endpgm222entry:223 %gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4224 call void @llvm.amdgcn.cluster.load.async.to.lds.b128(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 27, i32 %mask)225 ret void226}227 228define amdgpu_ps void @cluster_load_async_to_lds_b128_vaddr_imm_mask(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr) {229; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b128_vaddr_imm_mask:230; GFX1250-SDAG: ; %bb.0: ; %entry231; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1232; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]233; GFX1250-SDAG-NEXT: s_movk_i32 m0, 0x7f234; GFX1250-SDAG-NEXT: cluster_load_async_to_lds_b128 v2, v[0:1], off offset:16235; GFX1250-SDAG-NEXT: s_endpgm236;237; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b128_vaddr_imm_mask:238; GFX1250-GISEL: ; %bb.0: ; %entry239; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1240; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32241; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)242; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo243; GFX1250-GISEL-NEXT: s_movk_i32 m0, 0x7f244; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b128 v2, v[0:1], off offset:16245; GFX1250-GISEL-NEXT: s_endpgm246entry:247 %gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4248 call void @llvm.amdgcn.cluster.load.async.to.lds.b128(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 0, i32 127)249 ret void250}251 252define amdgpu_ps void @cluster_load_async_to_lds_b128_saddr(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask) {253; GFX1250-LABEL: cluster_load_async_to_lds_b128_saddr:254; GFX1250: ; %bb.0: ; %entry255; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1256; GFX1250-NEXT: v_mov_b32_e32 v1, 32257; GFX1250-NEXT: s_mov_b32 m0, s2258; GFX1250-NEXT: cluster_load_async_to_lds_b128 v0, v1, s[0:1] offset:16259; GFX1250-NEXT: s_endpgm260entry:261 %gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4262 call void @llvm.amdgcn.cluster.load.async.to.lds.b128(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 0, i32 %mask)263 ret void264}265 266define amdgpu_ps void @cluster_load_async_to_lds_b32_saddr_scale_offset(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask, i32 %idx) {267; GFX1250-LABEL: cluster_load_async_to_lds_b32_saddr_scale_offset:268; GFX1250: ; %bb.0: ; %entry269; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1270; GFX1250-NEXT: s_mov_b32 m0, s2271; GFX1250-NEXT: cluster_load_async_to_lds_b32 v0, v1, s[0:1] offset:16 scale_offset th:TH_LOAD_NT272; GFX1250-NEXT: s_endpgm273entry:274 %idxprom = sext i32 %idx to i64275 %gep = getelementptr i32, ptr addrspace(1) %gaddr, i64 %idxprom276 call void @llvm.amdgcn.cluster.load.async.to.lds.b32(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 1, i32 %mask)277 ret void278}279 280define amdgpu_ps void @cluster_load_async_to_lds_b64_saddr_scale_offset(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask, i32 %idx) {281; GFX1250-LABEL: cluster_load_async_to_lds_b64_saddr_scale_offset:282; GFX1250: ; %bb.0: ; %entry283; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1284; GFX1250-NEXT: s_mov_b32 m0, s2285; GFX1250-NEXT: cluster_load_async_to_lds_b64 v0, v1, s[0:1] offset:16 scale_offset th:TH_LOAD_NT286; GFX1250-NEXT: s_endpgm287entry:288 %idxprom = sext i32 %idx to i64289 %gep = getelementptr i64, ptr addrspace(1) %gaddr, i64 %idxprom290 call void @llvm.amdgcn.cluster.load.async.to.lds.b64(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 1, i32 %mask)291 ret void292}293 294define amdgpu_ps void @cluster_load_async_to_lds_b64_saddr_no_scale_offset(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask, i32 %idx) {295; GFX1250-LABEL: cluster_load_async_to_lds_b64_saddr_no_scale_offset:296; GFX1250: ; %bb.0: ; %entry297; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1298; GFX1250-NEXT: v_mov_b32_e32 v2, v1299; GFX1250-NEXT: s_mov_b32 m0, s2300; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)301; GFX1250-NEXT: v_ashrrev_i32_e32 v3, 31, v2302; GFX1250-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 2, s[0:1]303; GFX1250-NEXT: cluster_load_async_to_lds_b64 v0, v[2:3], off offset:16 th:TH_LOAD_NT304; GFX1250-NEXT: s_endpgm305entry:306 %idxprom = sext i32 %idx to i64307 %gep = getelementptr i32, ptr addrspace(1) %gaddr, i64 %idxprom308 call void @llvm.amdgcn.cluster.load.async.to.lds.b64(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 1, i32 %mask)309 ret void310}311