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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -O3 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s3; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -O3 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s4 5declare i32 @llvm.amdgcn.cluster.load.b32.i32.p1(ptr addrspace(1), i32 %cpol, i32 %mask)6declare <2 x i32> @llvm.amdgcn.cluster.load.b64.v2i32.p1(ptr addrspace(1), i32 %cpol, i32 %mask)7declare <4 x i32> @llvm.amdgcn.cluster.load.b128.v4i32.p1(ptr addrspace(1), i32 %cpol, i32 %mask)8 9define amdgpu_ps void @cluster_load_b32_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use, i32 %mask) {10; GFX1250-LABEL: cluster_load_b32_vaddr:11; GFX1250: ; %bb.0: ; %entry12; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 113; GFX1250-NEXT: v_readfirstlane_b32 s0, v414; GFX1250-NEXT: s_mov_b32 m0, s015; GFX1250-NEXT: cluster_load_b32 v0, v[0:1], off offset:32 th:TH_LOAD_NT16; GFX1250-NEXT: s_wait_loadcnt 0x017; GFX1250-NEXT: global_store_b32 v[2:3], v0, off18; GFX1250-NEXT: s_endpgm19entry:20 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 421 %val = call i32 @llvm.amdgcn.cluster.load.b32.i32.p1(ptr addrspace(1) %gep, i32 1, i32 %mask)22 store i32 %val, ptr addrspace(1) %use23 ret void24}25 26define amdgpu_ps void @cluster_load_b32_vaddr_imm_mask(ptr addrspace(1) %addr, ptr addrspace(1) %use) {27; GFX1250-LABEL: cluster_load_b32_vaddr_imm_mask:28; GFX1250: ; %bb.0: ; %entry29; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 130; GFX1250-NEXT: s_mov_b32 m0, 731; GFX1250-NEXT: cluster_load_b32 v0, v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE32; GFX1250-NEXT: s_wait_loadcnt 0x033; GFX1250-NEXT: global_store_b32 v[2:3], v0, off34; GFX1250-NEXT: s_endpgm35entry:36 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 437 %val = call i32 @llvm.amdgcn.cluster.load.b32.i32.p1(ptr addrspace(1) %gep, i32 10, i32 7)38 store i32 %val, ptr addrspace(1) %use39 ret void40}41 42define amdgpu_ps void @cluster_load_b32_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 inreg %mask) {43; GFX1250-LABEL: cluster_load_b32_saddr:44; GFX1250: ; %bb.0: ; %entry45; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 146; GFX1250-NEXT: v_mov_b32_e32 v2, 047; GFX1250-NEXT: s_mov_b32 m0, s248; GFX1250-NEXT: cluster_load_b32 v2, v2, s[0:1] offset:32 th:TH_LOAD_NT_HT scope:SCOPE_DEV49; GFX1250-NEXT: s_wait_loadcnt 0x050; GFX1250-NEXT: global_store_b32 v[0:1], v2, off51; GFX1250-NEXT: s_endpgm52entry:53 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 454 %val = call i32 @llvm.amdgcn.cluster.load.b32.i32.p1(ptr addrspace(1) %gep, i32 22, i32 %mask)55 store i32 %val, ptr addrspace(1) %use56 ret void57}58 59define amdgpu_ps void @cluster_load_monitor_b32_saddr_scale_offset(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 inreg %mask, i32 %idx) {60; GFX1250-LABEL: cluster_load_monitor_b32_saddr_scale_offset:61; GFX1250: ; %bb.0: ; %entry62; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 163; GFX1250-NEXT: s_mov_b32 m0, s264; GFX1250-NEXT: cluster_load_b32 v2, v2, s[0:1] scale_offset th:TH_LOAD_BYPASS scope:SCOPE_SYS65; GFX1250-NEXT: s_wait_loadcnt 0x066; GFX1250-NEXT: global_store_b32 v[0:1], v2, off67; GFX1250-NEXT: s_endpgm68entry:69 %idxprom = sext i32 %idx to i6470 %gep = getelementptr i32, ptr addrspace(1) %addr, i64 %idxprom71 %val = call i32 @llvm.amdgcn.cluster.load.b32.i32.p1(ptr addrspace(1) %gep, i32 27, i32 inreg %mask)72 store i32 %val, ptr addrspace(1) %use73 ret void74}75 76define amdgpu_ps void @cluster_load_b64_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use, i32 %mask) {77; GFX1250-LABEL: cluster_load_b64_vaddr:78; GFX1250: ; %bb.0: ; %entry79; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 180; GFX1250-NEXT: v_readfirstlane_b32 s0, v481; GFX1250-NEXT: s_mov_b32 m0, s082; GFX1250-NEXT: cluster_load_b64 v[0:1], v[0:1], off offset:32 th:TH_LOAD_NT83; GFX1250-NEXT: s_wait_loadcnt 0x084; GFX1250-NEXT: global_store_b64 v[2:3], v[0:1], off85; GFX1250-NEXT: s_endpgm86entry:87 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 488 %val = call <2 x i32> @llvm.amdgcn.cluster.load.b64.v2i32.p1(ptr addrspace(1) %gep, i32 1, i32 %mask)89 store <2 x i32> %val, ptr addrspace(1) %use90 ret void91}92 93define amdgpu_ps void @cluster_load_b64_vaddr_imm_mask(ptr addrspace(1) %addr, ptr addrspace(1) %use) {94; GFX1250-LABEL: cluster_load_b64_vaddr_imm_mask:95; GFX1250: ; %bb.0: ; %entry96; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 197; GFX1250-NEXT: s_mov_b32 m0, 0x1000798; GFX1250-NEXT: cluster_load_b64 v[0:1], v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE99; GFX1250-NEXT: s_wait_loadcnt 0x0100; GFX1250-NEXT: global_store_b64 v[2:3], v[0:1], off101; GFX1250-NEXT: s_endpgm102entry:103 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4104 %val = call <2 x i32> @llvm.amdgcn.cluster.load.b64.v2i32.p1(ptr addrspace(1) %gep, i32 10, i32 65543)105 store <2 x i32> %val, ptr addrspace(1) %use106 ret void107}108 109define amdgpu_ps void @cluster_load_b64_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 inreg %mask) {110; GFX1250-LABEL: cluster_load_b64_saddr:111; GFX1250: ; %bb.0: ; %entry112; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1113; GFX1250-NEXT: v_mov_b32_e32 v2, 0114; GFX1250-NEXT: s_mov_b32 m0, s2115; GFX1250-NEXT: cluster_load_b64 v[2:3], v2, s[0:1] offset:32 th:TH_LOAD_NT_HT scope:SCOPE_DEV116; GFX1250-NEXT: s_wait_loadcnt 0x0117; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off118; GFX1250-NEXT: s_endpgm119entry:120 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4121 %val = call <2 x i32> @llvm.amdgcn.cluster.load.b64.v2i32.p1(ptr addrspace(1) %gep, i32 22, i32 %mask)122 store <2 x i32> %val, ptr addrspace(1) %use123 ret void124}125 126define amdgpu_ps void @cluster_load_monitor_b64_saddr_scale_offset(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 inreg %mask, i32 %idx) {127; GFX1250-LABEL: cluster_load_monitor_b64_saddr_scale_offset:128; GFX1250: ; %bb.0: ; %entry129; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1130; GFX1250-NEXT: s_mov_b32 m0, s2131; GFX1250-NEXT: cluster_load_b64 v[2:3], v2, s[0:1] scale_offset th:TH_LOAD_BYPASS scope:SCOPE_SYS132; GFX1250-NEXT: s_wait_loadcnt 0x0133; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off134; GFX1250-NEXT: s_endpgm135entry:136 %idxprom = sext i32 %idx to i64137 %gep = getelementptr i64, ptr addrspace(1) %addr, i64 %idxprom138 %val = call <2 x i32> @llvm.amdgcn.cluster.load.b64.v2i32.p1(ptr addrspace(1) %gep, i32 27, i32 inreg %mask)139 store <2 x i32> %val, ptr addrspace(1) %use140 ret void141}142 143define amdgpu_ps void @cluster_load_b128_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use, i32 %mask) {144; GFX1250-LABEL: cluster_load_b128_vaddr:145; GFX1250: ; %bb.0: ; %entry146; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1147; GFX1250-NEXT: v_readfirstlane_b32 s0, v4148; GFX1250-NEXT: s_mov_b32 m0, s0149; GFX1250-NEXT: cluster_load_b128 v[4:7], v[0:1], off offset:32 th:TH_LOAD_NT150; GFX1250-NEXT: s_wait_loadcnt 0x0151; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off152; GFX1250-NEXT: s_endpgm153entry:154 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4155 %val = call <4 x i32> @llvm.amdgcn.cluster.load.b128.v4i32.p1(ptr addrspace(1) %gep, i32 1, i32 %mask)156 store <4 x i32> %val, ptr addrspace(1) %use157 ret void158}159 160define amdgpu_ps void @cluster_load_b128_vaddr_imm_mask(ptr addrspace(1) %addr, ptr addrspace(1) %use) {161; GFX1250-LABEL: cluster_load_b128_vaddr_imm_mask:162; GFX1250: ; %bb.0: ; %entry163; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1164; GFX1250-NEXT: s_mov_b32 m0, 15165; GFX1250-NEXT: cluster_load_b128 v[4:7], v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE166; GFX1250-NEXT: s_wait_loadcnt 0x0167; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off168; GFX1250-NEXT: s_endpgm169entry:170 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4171 %val = call <4 x i32> @llvm.amdgcn.cluster.load.b128.v4i32.p1(ptr addrspace(1) %gep, i32 10, i32 15)172 store <4 x i32> %val, ptr addrspace(1) %use173 ret void174}175 176define amdgpu_ps void @cluster_load_b128_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 inreg %mask) {177; GFX1250-LABEL: cluster_load_b128_saddr:178; GFX1250: ; %bb.0: ; %entry179; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1180; GFX1250-NEXT: v_mov_b32_e32 v2, 0181; GFX1250-NEXT: s_mov_b32 m0, s2182; GFX1250-NEXT: cluster_load_b128 v[2:5], v2, s[0:1] offset:32 th:TH_LOAD_BYPASS scope:SCOPE_SYS183; GFX1250-NEXT: s_wait_loadcnt 0x0184; GFX1250-NEXT: global_store_b128 v[0:1], v[2:5], off185; GFX1250-NEXT: s_endpgm186entry:187 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4188 %val = call <4 x i32> @llvm.amdgcn.cluster.load.b128.v4i32.p1(ptr addrspace(1) %gep, i32 27, i32 inreg %mask)189 store <4 x i32> %val, ptr addrspace(1) %use190 ret void191}192;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:193; GFX1250-GISEL: {{.*}}194; GFX1250-SDAG: {{.*}}195