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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG-REAL16 %s3; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG-FAKE16 %s4; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-REAL16 %s5; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-FAKE16 %s6 7declare half @llvm.amdgcn.cvt.f16.bf8(i32, i32)8declare half @llvm.amdgcn.cvt.f16.fp8(i32, i32)9declare <2 x half> @llvm.amdgcn.cvt.pk.f16.bf8(i16)10declare <2 x half> @llvm.amdgcn.cvt.pk.f16.fp8(i16)11 12define amdgpu_ps float @test_cvt_f16_bf8_byte0(i32 %a) {13; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_bf8_byte0:14; GFX1250-SDAG-REAL16: ; %bb.0:15; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 116; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_bf8_e32 v0.l, v017; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)18; GFX1250-SDAG-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l19; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog20;21; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_bf8_byte0:22; GFX1250-SDAG-FAKE16: ; %bb.0:23; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 124; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_bf8_e32 v0, v025; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)26; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v027; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog28;29; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_bf8_byte0:30; GFX1250-GISEL-REAL16: ; %bb.0:31; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 132; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_bf8_e32 v0.l, v033; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)34; GFX1250-GISEL-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l35; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog36;37; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_bf8_byte0:38; GFX1250-GISEL-FAKE16: ; %bb.0:39; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 140; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_bf8_e32 v0, v041; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)42; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v043; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog44 %cvt = tail call half @llvm.amdgcn.cvt.f16.bf8(i32 %a, i32 0)45 %ret = fpext half %cvt to float46 ret float %ret47}48 49define amdgpu_ps float @test_cvt_f16_bf8_byte1(i32 %a) {50; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_bf8_byte1:51; GFX1250-SDAG-REAL16: ; %bb.0:52; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 153; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.l, v0 byte_sel:154; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)55; GFX1250-SDAG-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l56; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog57;58; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_bf8_byte1:59; GFX1250-SDAG-FAKE16: ; %bb.0:60; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 161; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_bf8_e64 v0, v0 byte_sel:162; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)63; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v064; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog65;66; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_bf8_byte1:67; GFX1250-GISEL-REAL16: ; %bb.0:68; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 169; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.l, v0 byte_sel:170; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)71; GFX1250-GISEL-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l72; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog73;74; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_bf8_byte1:75; GFX1250-GISEL-FAKE16: ; %bb.0:76; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 177; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_bf8_e64 v0, v0 byte_sel:178; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)79; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v080; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog81 %cvt = tail call half @llvm.amdgcn.cvt.f16.bf8(i32 %a, i32 1)82 %ret = fpext half %cvt to float83 ret float %ret84}85 86define amdgpu_ps float @test_cvt_f16_bf8_byte2(i32 %a) {87; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_bf8_byte2:88; GFX1250-SDAG-REAL16: ; %bb.0:89; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 190; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.l, v0 byte_sel:291; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)92; GFX1250-SDAG-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l93; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog94;95; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_bf8_byte2:96; GFX1250-SDAG-FAKE16: ; %bb.0:97; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 198; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_bf8_e64 v0, v0 byte_sel:299; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)100; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0101; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog102;103; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_bf8_byte2:104; GFX1250-GISEL-REAL16: ; %bb.0:105; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1106; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.l, v0 byte_sel:2107; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)108; GFX1250-GISEL-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l109; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog110;111; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_bf8_byte2:112; GFX1250-GISEL-FAKE16: ; %bb.0:113; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1114; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_bf8_e64 v0, v0 byte_sel:2115; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)116; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0117; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog118 %cvt = tail call half @llvm.amdgcn.cvt.f16.bf8(i32 %a, i32 2)119 %ret = fpext half %cvt to float120 ret float %ret121}122 123define amdgpu_ps float @test_cvt_f16_bf8_byte3(i32 %a) {124; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_bf8_byte3:125; GFX1250-SDAG-REAL16: ; %bb.0:126; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1127; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.l, v0 byte_sel:3128; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)129; GFX1250-SDAG-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l130; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog131;132; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_bf8_byte3:133; GFX1250-SDAG-FAKE16: ; %bb.0:134; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1135; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_bf8_e64 v0, v0 byte_sel:3136; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)137; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0138; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog139;140; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_bf8_byte3:141; GFX1250-GISEL-REAL16: ; %bb.0:142; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1143; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.l, v0 byte_sel:3144; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)145; GFX1250-GISEL-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l146; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog147;148; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_bf8_byte3:149; GFX1250-GISEL-FAKE16: ; %bb.0:150; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1151; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_bf8_e64 v0, v0 byte_sel:3152; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)153; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0154; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog155 %cvt = tail call half @llvm.amdgcn.cvt.f16.bf8(i32 %a, i32 3)156 %ret = fpext half %cvt to float157 ret float %ret158}159 160define amdgpu_ps float @test_cvt_f16_bf8_byte3_hi(i32 %a) {161; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_bf8_byte3_hi:162; GFX1250-SDAG-REAL16: ; %bb.0:163; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1164; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.h, v0 byte_sel:3165; GFX1250-SDAG-REAL16-NEXT: v_mov_b16_e32 v0.l, 0166; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog167;168; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_bf8_byte3_hi:169; GFX1250-SDAG-FAKE16: ; %bb.0:170; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1171; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_bf8_e64 v0, v0 byte_sel:3172; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)173; GFX1250-SDAG-FAKE16-NEXT: v_perm_b32 v0, v0, 0, 0x5040100174; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog175;176; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_bf8_byte3_hi:177; GFX1250-GISEL-REAL16: ; %bb.0:178; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1179; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.l, v0 byte_sel:3180; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)181; GFX1250-GISEL-REAL16-NEXT: v_lshl_or_b32 v0, v0, 16, 0182; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog183;184; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_bf8_byte3_hi:185; GFX1250-GISEL-FAKE16: ; %bb.0:186; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1187; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_bf8_e64 v0, v0 byte_sel:3188; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)189; GFX1250-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, 0190; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog191 %cvt = tail call half @llvm.amdgcn.cvt.f16.bf8(i32 %a, i32 3)192 %ins.0 = insertelement <2 x half> undef, half 0.0, i32 0193 %ins.1 = insertelement <2 x half> %ins.0, half %cvt, i32 1194 %ret = bitcast <2 x half> %ins.1 to float195 ret float %ret196}197 198define amdgpu_ps float @test_cvt_f16_fp8_byte0(i32 %a) {199; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_fp8_byte0:200; GFX1250-SDAG-REAL16: ; %bb.0:201; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1202; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_fp8_e32 v0.l, v0203; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)204; GFX1250-SDAG-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l205; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog206;207; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_fp8_byte0:208; GFX1250-SDAG-FAKE16: ; %bb.0:209; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1210; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_fp8_e32 v0, v0211; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)212; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0213; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog214;215; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_fp8_byte0:216; GFX1250-GISEL-REAL16: ; %bb.0:217; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1218; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_fp8_e32 v0.l, v0219; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)220; GFX1250-GISEL-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l221; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog222;223; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_fp8_byte0:224; GFX1250-GISEL-FAKE16: ; %bb.0:225; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1226; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_fp8_e32 v0, v0227; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)228; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0229; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog230 %cvt = tail call half @llvm.amdgcn.cvt.f16.fp8(i32 %a, i32 0)231 %ret = fpext half %cvt to float232 ret float %ret233}234 235define amdgpu_ps float @test_cvt_f16_fp8_byte1(i32 %a) {236; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_fp8_byte1:237; GFX1250-SDAG-REAL16: ; %bb.0:238; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1239; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.l, v0 byte_sel:1240; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)241; GFX1250-SDAG-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l242; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog243;244; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_fp8_byte1:245; GFX1250-SDAG-FAKE16: ; %bb.0:246; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1247; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_fp8_e64 v0, v0 byte_sel:1248; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)249; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0250; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog251;252; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_fp8_byte1:253; GFX1250-GISEL-REAL16: ; %bb.0:254; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1255; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.l, v0 byte_sel:1256; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)257; GFX1250-GISEL-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l258; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog259;260; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_fp8_byte1:261; GFX1250-GISEL-FAKE16: ; %bb.0:262; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1263; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_fp8_e64 v0, v0 byte_sel:1264; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)265; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0266; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog267 %cvt = tail call half @llvm.amdgcn.cvt.f16.fp8(i32 %a, i32 1)268 %ret = fpext half %cvt to float269 ret float %ret270}271 272define amdgpu_ps float @test_cvt_f16_fp8_byte2(i32 %a) {273; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_fp8_byte2:274; GFX1250-SDAG-REAL16: ; %bb.0:275; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1276; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.l, v0 byte_sel:2277; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)278; GFX1250-SDAG-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l279; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog280;281; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_fp8_byte2:282; GFX1250-SDAG-FAKE16: ; %bb.0:283; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1284; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_fp8_e64 v0, v0 byte_sel:2285; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)286; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0287; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog288;289; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_fp8_byte2:290; GFX1250-GISEL-REAL16: ; %bb.0:291; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1292; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.l, v0 byte_sel:2293; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)294; GFX1250-GISEL-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l295; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog296;297; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_fp8_byte2:298; GFX1250-GISEL-FAKE16: ; %bb.0:299; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1300; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_fp8_e64 v0, v0 byte_sel:2301; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)302; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0303; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog304 %cvt = tail call half @llvm.amdgcn.cvt.f16.fp8(i32 %a, i32 2)305 %ret = fpext half %cvt to float306 ret float %ret307}308 309define amdgpu_ps float @test_cvt_f16_fp8_byte3(i32 %a) {310; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_fp8_byte3:311; GFX1250-SDAG-REAL16: ; %bb.0:312; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1313; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.l, v0 byte_sel:3314; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)315; GFX1250-SDAG-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l316; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog317;318; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_fp8_byte3:319; GFX1250-SDAG-FAKE16: ; %bb.0:320; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1321; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_fp8_e64 v0, v0 byte_sel:3322; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)323; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0324; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog325;326; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_fp8_byte3:327; GFX1250-GISEL-REAL16: ; %bb.0:328; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1329; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.l, v0 byte_sel:3330; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)331; GFX1250-GISEL-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l332; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog333;334; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_fp8_byte3:335; GFX1250-GISEL-FAKE16: ; %bb.0:336; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1337; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_fp8_e64 v0, v0 byte_sel:3338; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)339; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0340; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog341 %cvt = tail call half @llvm.amdgcn.cvt.f16.fp8(i32 %a, i32 3)342 %ret = fpext half %cvt to float343 ret float %ret344}345 346define amdgpu_ps float @test_cvt_f16_fp8_byte3_hi(i32 %a) {347; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_fp8_byte3_hi:348; GFX1250-SDAG-REAL16: ; %bb.0:349; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1350; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.h, v0 byte_sel:3351; GFX1250-SDAG-REAL16-NEXT: v_mov_b16_e32 v0.l, 0352; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog353;354; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_fp8_byte3_hi:355; GFX1250-SDAG-FAKE16: ; %bb.0:356; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1357; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_fp8_e64 v0, v0 byte_sel:3358; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)359; GFX1250-SDAG-FAKE16-NEXT: v_perm_b32 v0, v0, 0, 0x5040100360; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog361;362; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_fp8_byte3_hi:363; GFX1250-GISEL-REAL16: ; %bb.0:364; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1365; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.l, v0 byte_sel:3366; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)367; GFX1250-GISEL-REAL16-NEXT: v_lshl_or_b32 v0, v0, 16, 0368; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog369;370; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_fp8_byte3_hi:371; GFX1250-GISEL-FAKE16: ; %bb.0:372; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1373; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_fp8_e64 v0, v0 byte_sel:3374; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)375; GFX1250-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, 0376; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog377 %cvt = tail call half @llvm.amdgcn.cvt.f16.fp8(i32 %a, i32 3)378 %ins.0 = insertelement <2 x half> undef, half 0.0, i32 0379 %ins.1 = insertelement <2 x half> %ins.0, half %cvt, i32 1380 %ret = bitcast <2 x half> %ins.1 to float381 ret float %ret382}383 384define amdgpu_ps float @test_cvt_pk_f16_bf8_v(i16 %a) {385; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_f16_bf8_v:386; GFX1250-SDAG-REAL16: ; %bb.0:387; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1388; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_f16_bf8 v0, v0.l389; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog390;391; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_f16_bf8_v:392; GFX1250-SDAG-FAKE16: ; %bb.0:393; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1394; GFX1250-SDAG-FAKE16-NEXT: v_cvt_pk_f16_bf8 v0, v0395; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog396;397; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_f16_bf8_v:398; GFX1250-GISEL-REAL16: ; %bb.0:399; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1400; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_f16_bf8 v0, v0.l401; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog402;403; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_f16_bf8_v:404; GFX1250-GISEL-FAKE16: ; %bb.0:405; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1406; GFX1250-GISEL-FAKE16-NEXT: v_cvt_pk_f16_bf8 v0, v0407; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog408 %cvt = tail call <2 x half> @llvm.amdgcn.cvt.pk.f16.bf8(i16 %a)409 %ret = bitcast <2 x half> %cvt to float410 ret float %ret411}412 413define amdgpu_ps float @test_cvt_pk_f16_bf8_s(i16 inreg %a) {414; GFX1250-LABEL: test_cvt_pk_f16_bf8_s:415; GFX1250: ; %bb.0:416; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1417; GFX1250-NEXT: v_cvt_pk_f16_bf8 v0, s0418; GFX1250-NEXT: ; return to shader part epilog419 %cvt = tail call <2 x half> @llvm.amdgcn.cvt.pk.f16.bf8(i16 %a)420 %ret = bitcast <2 x half> %cvt to float421 ret float %ret422}423 424define amdgpu_ps float @test_cvt_pk_f16_fp8_v(i16 %a) {425; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_f16_fp8_v:426; GFX1250-SDAG-REAL16: ; %bb.0:427; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1428; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_f16_fp8 v0, v0.l429; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog430;431; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_f16_fp8_v:432; GFX1250-SDAG-FAKE16: ; %bb.0:433; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1434; GFX1250-SDAG-FAKE16-NEXT: v_cvt_pk_f16_fp8 v0, v0435; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog436;437; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_f16_fp8_v:438; GFX1250-GISEL-REAL16: ; %bb.0:439; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1440; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_f16_fp8 v0, v0.l441; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog442;443; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_f16_fp8_v:444; GFX1250-GISEL-FAKE16: ; %bb.0:445; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1446; GFX1250-GISEL-FAKE16-NEXT: v_cvt_pk_f16_fp8 v0, v0447; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog448 %cvt = tail call <2 x half> @llvm.amdgcn.cvt.pk.f16.fp8(i16 %a)449 %ret = bitcast <2 x half> %cvt to float450 ret float %ret451}452 453define amdgpu_ps float @test_cvt_pk_f16_fp8_s(i16 inreg %a) {454; GFX1250-LABEL: test_cvt_pk_f16_fp8_s:455; GFX1250: ; %bb.0:456; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1457; GFX1250-NEXT: v_cvt_pk_f16_fp8 v0, s0458; GFX1250-NEXT: ; return to shader part epilog459 %cvt = tail call <2 x half> @llvm.amdgcn.cvt.pk.f16.fp8(i16 %a)460 %ret = bitcast <2 x half> %cvt to float461 ret float %ret462}463 464define amdgpu_ps float @test_cvt_pk_f16_fp8_v_hi(<2 x i16> %a) {465; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_f16_fp8_v_hi:466; GFX1250-SDAG-REAL16: ; %bb.0:467; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1468; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_f16_fp8 v0, v0.h469; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog470;471; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_f16_fp8_v_hi:472; GFX1250-SDAG-FAKE16: ; %bb.0:473; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1474; GFX1250-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0475; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)476; GFX1250-SDAG-FAKE16-NEXT: v_cvt_pk_f16_fp8 v0, v0477; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog478;479; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_f16_fp8_v_hi:480; GFX1250-GISEL-REAL16: ; %bb.0:481; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1482; GFX1250-GISEL-REAL16-NEXT: v_lshrrev_b32_e32 v0, 16, v0483; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)484; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_f16_fp8 v0, v0.l485; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog486;487; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_f16_fp8_v_hi:488; GFX1250-GISEL-FAKE16: ; %bb.0:489; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1490; GFX1250-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0491; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)492; GFX1250-GISEL-FAKE16-NEXT: v_cvt_pk_f16_fp8 v0, v0493; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog494 %a.1 = extractelement <2 x i16> %a, i32 1495 %cvt = tail call <2 x half> @llvm.amdgcn.cvt.pk.f16.fp8(i16 %a.1)496 %ret = bitcast <2 x half> %cvt to float497 ret float %ret498}499