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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250 %s4 5define amdgpu_cs float @test_cvt_f32_bf8_byte0(i32 %a) {6; GFX12-LABEL: test_cvt_f32_bf8_byte0:7; GFX12: ; %bb.0:8; GFX12-NEXT: v_cvt_f32_bf8_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:19; GFX12-NEXT: ; return to shader part epilog10;11; GFX1250-LABEL: test_cvt_f32_bf8_byte0:12; GFX1250: ; %bb.0:13; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 114; GFX1250-NEXT: v_cvt_f32_bf8_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:115; GFX1250-NEXT: ; return to shader part epilog16 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %a, i32 228, i32 15, i32 15, i1 1)17 %ret = tail call float @llvm.amdgcn.cvt.f32.bf8(i32 %tmp0, i32 0)18 ret float %ret19}20 21define amdgpu_cs float @test_cvt_f32_bf8_byte1(i32 %a) {22; GFX12-LABEL: test_cvt_f32_bf8_byte1:23; GFX12: ; %bb.0:24; GFX12-NEXT: v_cvt_f32_bf8_e64_dpp v0, v0 byte_sel:1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:125; GFX12-NEXT: ; return to shader part epilog26;27; GFX1250-LABEL: test_cvt_f32_bf8_byte1:28; GFX1250: ; %bb.0:29; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 130; GFX1250-NEXT: v_cvt_f32_bf8_e64_dpp v0, v0 byte_sel:1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:131; GFX1250-NEXT: ; return to shader part epilog32 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %a, i32 228, i32 15, i32 15, i1 1)33 %ret = tail call float @llvm.amdgcn.cvt.f32.bf8(i32 %tmp0, i32 1)34 ret float %ret35}36 37define amdgpu_cs float @test_cvt_f32_bf8_byte2(i32 %a) {38; GFX12-LABEL: test_cvt_f32_bf8_byte2:39; GFX12: ; %bb.0:40; GFX12-NEXT: v_cvt_f32_bf8_e64_dpp v0, v0 byte_sel:2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:141; GFX12-NEXT: ; return to shader part epilog42;43; GFX1250-LABEL: test_cvt_f32_bf8_byte2:44; GFX1250: ; %bb.0:45; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 146; GFX1250-NEXT: v_cvt_f32_bf8_e64_dpp v0, v0 byte_sel:2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:147; GFX1250-NEXT: ; return to shader part epilog48 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %a, i32 228, i32 15, i32 15, i1 1)49 %ret = tail call float @llvm.amdgcn.cvt.f32.bf8(i32 %tmp0, i32 2)50 ret float %ret51}52 53define amdgpu_cs float @test_cvt_f32_fp8_byte3(i32 %a) {54; GFX12-LABEL: test_cvt_f32_fp8_byte3:55; GFX12: ; %bb.0:56; GFX12-NEXT: v_cvt_f32_fp8_e64_dpp v0, v0 byte_sel:3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:157; GFX12-NEXT: ; return to shader part epilog58;59; GFX1250-LABEL: test_cvt_f32_fp8_byte3:60; GFX1250: ; %bb.0:61; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 162; GFX1250-NEXT: v_cvt_f32_fp8_e64_dpp v0, v0 byte_sel:3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:163; GFX1250-NEXT: ; return to shader part epilog64 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %a, i32 228, i32 15, i32 15, i1 1)65 %ret = tail call float @llvm.amdgcn.cvt.f32.fp8(i32 %tmp0, i32 3)66 ret float %ret67}68 69define amdgpu_cs void @test_cvt_pk_bf8_f32_word0(i32 %a, float %y, i32 %old, ptr addrspace(1) %out) {70; GFX12-LABEL: test_cvt_pk_bf8_f32_word0:71; GFX12: ; %bb.0:72; GFX12-NEXT: v_cvt_pk_bf8_f32_e64_dpp v2, v0, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:173; GFX12-NEXT: global_store_b32 v[3:4], v2, off74; GFX12-NEXT: s_endpgm75;76; GFX1250-LABEL: test_cvt_pk_bf8_f32_word0:77; GFX1250: ; %bb.0:78; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 179; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v380; GFX1250-NEXT: v_cvt_pk_bf8_f32_e64_dpp v2, v0, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:181; GFX1250-NEXT: global_store_b32 v[4:5], v2, off82; GFX1250-NEXT: s_endpgm83 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %a, i32 228, i32 15, i32 15, i1 1)84 %tmp1 = bitcast i32 %tmp0 to float85 %ret = tail call i32 @llvm.amdgcn.cvt.pk.bf8.f32(float %tmp1, float %y, i32 %old, i1 false)86 store i32 %ret, ptr addrspace(1) %out87 ret void88}89 90define amdgpu_cs void @test_cvt_pk_fp8_f32_word1(i32 %a, float %y, i32 %old, ptr addrspace(1) %out) {91; GFX12-LABEL: test_cvt_pk_fp8_f32_word1:92; GFX12: ; %bb.0:93; GFX12-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:194; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)95; GFX12-NEXT: v_cvt_pk_fp8_f32 v2, v0, v1 op_sel:[0,0,1]96; GFX12-NEXT: global_store_b32 v[3:4], v2, off97; GFX12-NEXT: s_endpgm98;99; GFX1250-LABEL: test_cvt_pk_fp8_f32_word1:100; GFX1250: ; %bb.0:101; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1102; GFX1250-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1103; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3104; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2)105; GFX1250-NEXT: v_cvt_pk_fp8_f32 v2, v0, v1 op_sel:[0,0,1]106; GFX1250-NEXT: global_store_b32 v[4:5], v2, off107; GFX1250-NEXT: s_endpgm108 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %a, i32 228, i32 15, i32 15, i1 1)109 %tmp1 = bitcast i32 %tmp0 to float110 %ret = tail call i32 @llvm.amdgcn.cvt.pk.fp8.f32(float %tmp1, float %y, i32 %old, i1 true)111 store i32 %ret, ptr addrspace(1) %out112 ret void113}114 115define amdgpu_cs void @test_cvt_sr_bf8_f32_byte0(i32 %a, i32 %r, i32 %old, ptr addrspace(1) %out) {116; GFX12-LABEL: test_cvt_sr_bf8_f32_byte0:117; GFX12: ; %bb.0:118; GFX12-NEXT: v_cvt_sr_bf8_f32_e64_dpp v2, v0, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1119; GFX12-NEXT: global_store_b32 v[3:4], v2, off120; GFX12-NEXT: s_endpgm121;122; GFX1250-LABEL: test_cvt_sr_bf8_f32_byte0:123; GFX1250: ; %bb.0:124; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1125; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3126; GFX1250-NEXT: v_cvt_sr_bf8_f32_e64_dpp v2, v0, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1127; GFX1250-NEXT: global_store_b32 v[4:5], v2, off128; GFX1250-NEXT: s_endpgm129 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %a, i32 228, i32 15, i32 15, i1 1)130 %tmp1 = bitcast i32 %tmp0 to float131 %ret = tail call i32 @llvm.amdgcn.cvt.sr.bf8.f32(float %tmp1, i32 %r, i32 %old, i32 0)132 store i32 %ret, ptr addrspace(1) %out133 ret void134}135 136define amdgpu_cs void @test_cvt_sr_fp8_f32_byte1(i32 %a, i32 %r, i32 %old, ptr addrspace(1) %out) {137; GFX12-LABEL: test_cvt_sr_fp8_f32_byte1:138; GFX12: ; %bb.0:139; GFX12-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1140; GFX12-NEXT: global_store_b32 v[3:4], v2, off141; GFX12-NEXT: s_endpgm142;143; GFX1250-LABEL: test_cvt_sr_fp8_f32_byte1:144; GFX1250: ; %bb.0:145; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1146; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3147; GFX1250-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1148; GFX1250-NEXT: global_store_b32 v[4:5], v2, off149; GFX1250-NEXT: s_endpgm150 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %a, i32 228, i32 15, i32 15, i1 1)151 %tmp1 = bitcast i32 %tmp0 to float152 %ret = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f32(float %tmp1, i32 %r, i32 %old, i32 1)153 store i32 %ret, ptr addrspace(1) %out154 ret void155}156 157define amdgpu_cs void @test_cvt_sr_fp8_f32_byte2(i32 %a, i32 %r, i32 %old, ptr addrspace(1) %out) {158; GFX12-LABEL: test_cvt_sr_fp8_f32_byte2:159; GFX12: ; %bb.0:160; GFX12-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1161; GFX12-NEXT: global_store_b32 v[3:4], v2, off162; GFX12-NEXT: s_endpgm163;164; GFX1250-LABEL: test_cvt_sr_fp8_f32_byte2:165; GFX1250: ; %bb.0:166; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1167; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3168; GFX1250-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1169; GFX1250-NEXT: global_store_b32 v[4:5], v2, off170; GFX1250-NEXT: s_endpgm171 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %a, i32 228, i32 15, i32 15, i1 1)172 %tmp1 = bitcast i32 %tmp0 to float173 %ret = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f32(float %tmp1, i32 %r, i32 %old, i32 2)174 store i32 %ret, ptr addrspace(1) %out175 ret void176}177 178declare float @llvm.amdgcn.cvt.f32.bf8(i32, i32)179declare float @llvm.amdgcn.cvt.f32.fp8(i32, i32)180declare i32 @llvm.amdgcn.cvt.pk.bf8.f32(float, float, i32, i1)181declare i32 @llvm.amdgcn.cvt.pk.fp8.f32(float, float, i32, i1)182declare i32 @llvm.amdgcn.cvt.sr.bf8.f32(float, i32, i32, i32)183declare i32 @llvm.amdgcn.cvt.sr.fp8.f32(float, i32, i32, i32)184 185declare i32 @llvm.amdgcn.mov.dpp.i32(i32, i32, i32, i32, i1) #1186declare i32 @llvm.amdgcn.mov.dpp8.i32(i32, i32) #1187 188attributes #0 = { nounwind convergent }189attributes #1 = { nounwind readnone convergent }190