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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-TRUE16 %s3; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s4; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s5 6declare i32 @llvm.amdgcn.cvt.pk.fp8.f32.e5m3(float, float, i32, i1)7declare i32 @llvm.amdgcn.cvt.sr.fp8.f32.e5m3(float, i32, i32, i32)8declare float @llvm.amdgcn.cvt.f32.fp8.e5m3(i32, i32)9 10define i32 @test_cvt_pk_fp8_f32_word0(float %x, float %y, i32 %old) {11; GFX1250-TRUE16-LABEL: test_cvt_pk_fp8_f32_word0:12; GFX1250-TRUE16: ; %bb.0:13; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x014; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x015; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v2.l, v0, v1 clamp16; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)17; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v0, v218; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]19;20; GFX1250-FAKE16-LABEL: test_cvt_pk_fp8_f32_word0:21; GFX1250-FAKE16: ; %bb.0:22; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x023; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x024; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v2, v0, v1 clamp25; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)26; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, v227; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]28;29; GFX1250-GISEL-LABEL: test_cvt_pk_fp8_f32_word0:30; GFX1250-GISEL: ; %bb.0:31; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x032; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x033; GFX1250-GISEL-NEXT: v_cvt_pk_fp8_f32 v2, v0, v1 clamp34; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)35; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, v236; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]37 %ret = tail call i32 @llvm.amdgcn.cvt.pk.fp8.f32.e5m3(float %x, float %y, i32 %old, i1 false)38 ret i32 %ret39}40 41define i32 @test_cvt_pk_fp8_f32_word1(float %x, float %y, i32 %old) {42; GFX1250-TRUE16-LABEL: test_cvt_pk_fp8_f32_word1:43; GFX1250-TRUE16: ; %bb.0:44; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x045; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x046; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v2.h, v0, v1 op_sel:[0,0,1] clamp47; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)48; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v0, v249; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]50;51; GFX1250-FAKE16-LABEL: test_cvt_pk_fp8_f32_word1:52; GFX1250-FAKE16: ; %bb.0:53; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x054; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x055; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v2, v0, v1 op_sel:[0,0,1] clamp56; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)57; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, v258; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]59;60; GFX1250-GISEL-LABEL: test_cvt_pk_fp8_f32_word1:61; GFX1250-GISEL: ; %bb.0:62; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x063; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x064; GFX1250-GISEL-NEXT: v_cvt_pk_fp8_f32 v2, v0, v1 op_sel:[0,0,1] clamp65; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)66; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, v267; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]68 %ret = tail call i32 @llvm.amdgcn.cvt.pk.fp8.f32.e5m3(float %x, float %y, i32 %old, i1 true)69 ret i32 %ret70}71 72define amdgpu_cs void @test_cvt_pk_fp8_f32_word1_dpp(i32 %a, float %y, i32 %old, ptr addrspace(1) %out) {73; GFX1250-TRUE16-LABEL: test_cvt_pk_fp8_f32_word1_dpp:74; GFX1250-TRUE16: ; %bb.0:75; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 176; GFX1250-TRUE16-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:177; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v378; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)79; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v2.h, v0, v1 op_sel:[0,0,1] clamp80; GFX1250-TRUE16-NEXT: global_store_b32 v[4:5], v2, off81; GFX1250-TRUE16-NEXT: s_endpgm82;83; GFX1250-FAKE16-LABEL: test_cvt_pk_fp8_f32_word1_dpp:84; GFX1250-FAKE16: ; %bb.0:85; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 186; GFX1250-FAKE16-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:187; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v388; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)89; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v2, v0, v1 op_sel:[0,0,1] clamp90; GFX1250-FAKE16-NEXT: global_store_b32 v[4:5], v2, off91; GFX1250-FAKE16-NEXT: s_endpgm92;93; GFX1250-GISEL-LABEL: test_cvt_pk_fp8_f32_word1_dpp:94; GFX1250-GISEL: ; %bb.0:95; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 196; GFX1250-GISEL-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:197; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v498; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)99; GFX1250-GISEL-NEXT: v_cvt_pk_fp8_f32 v2, v0, v1 op_sel:[0,0,1] clamp100; GFX1250-GISEL-NEXT: global_store_b32 v[6:7], v2, off101; GFX1250-GISEL-NEXT: s_endpgm102 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %a, i32 228, i32 15, i32 15, i1 1)103 %tmp1 = bitcast i32 %tmp0 to float104 %ret = tail call i32 @llvm.amdgcn.cvt.pk.fp8.f32.e5m3(float %tmp1, float %y, i32 %old, i1 true)105 store i32 %ret, ptr addrspace(1) %out106 ret void107}108 109define i32 @test_cvt_sr_fp8_f32_byte0(float %x, i32 %r, i32 %old) {110; GFX1250-LABEL: test_cvt_sr_fp8_f32_byte0:111; GFX1250: ; %bb.0:112; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0113; GFX1250-NEXT: s_wait_kmcnt 0x0114; GFX1250-NEXT: v_cvt_sr_fp8_f32 v2, v0, v1 clamp115; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)116; GFX1250-NEXT: v_mov_b32_e32 v0, v2117; GFX1250-NEXT: s_set_pc_i64 s[30:31]118 %ret = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f32.e5m3(float %x, i32 %r, i32 %old, i32 0)119 ret i32 %ret120}121 122define i32 @test_cvt_sr_fp8_f32_byte1(float %x, i32 %r, i32 %old) {123; GFX1250-LABEL: test_cvt_sr_fp8_f32_byte1:124; GFX1250: ; %bb.0:125; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0126; GFX1250-NEXT: s_wait_kmcnt 0x0127; GFX1250-NEXT: v_cvt_sr_fp8_f32 v2, v0, v1 byte_sel:1 clamp128; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)129; GFX1250-NEXT: v_mov_b32_e32 v0, v2130; GFX1250-NEXT: s_set_pc_i64 s[30:31]131 %ret = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f32.e5m3(float %x, i32 %r, i32 %old, i32 1)132 ret i32 %ret133}134 135define i32 @test_cvt_sr_fp8_f32_byte2(float %x, i32 %r, i32 %old) {136; GFX1250-LABEL: test_cvt_sr_fp8_f32_byte2:137; GFX1250: ; %bb.0:138; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0139; GFX1250-NEXT: s_wait_kmcnt 0x0140; GFX1250-NEXT: v_cvt_sr_fp8_f32 v2, v0, v1 byte_sel:2 clamp141; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)142; GFX1250-NEXT: v_mov_b32_e32 v0, v2143; GFX1250-NEXT: s_set_pc_i64 s[30:31]144 %ret = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f32.e5m3(float %x, i32 %r, i32 %old, i32 2)145 ret i32 %ret146}147 148define i32 @test_cvt_sr_fp8_f32_byte3(float %x, i32 %r, i32 %old) {149; GFX1250-LABEL: test_cvt_sr_fp8_f32_byte3:150; GFX1250: ; %bb.0:151; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0152; GFX1250-NEXT: s_wait_kmcnt 0x0153; GFX1250-NEXT: v_cvt_sr_fp8_f32 v2, v0, v1 byte_sel:3 clamp154; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)155; GFX1250-NEXT: v_mov_b32_e32 v0, v2156; GFX1250-NEXT: s_set_pc_i64 s[30:31]157 %ret = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f32.e5m3(float %x, i32 %r, i32 %old, i32 3)158 ret i32 %ret159}160 161define amdgpu_cs void @test_cvt_sr_fp8_f32_byte1_dpp(i32 %a, i32 %r, i32 %old, ptr addrspace(1) %out) {162; GFX1250-TRUE16-LABEL: test_cvt_sr_fp8_f32_byte1_dpp:163; GFX1250-TRUE16: ; %bb.0:164; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1165; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3166; GFX1250-TRUE16-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:1 clamp quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1167; GFX1250-TRUE16-NEXT: global_store_b32 v[4:5], v2, off168; GFX1250-TRUE16-NEXT: s_endpgm169;170; GFX1250-FAKE16-LABEL: test_cvt_sr_fp8_f32_byte1_dpp:171; GFX1250-FAKE16: ; %bb.0:172; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1173; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3174; GFX1250-FAKE16-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:1 clamp quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1175; GFX1250-FAKE16-NEXT: global_store_b32 v[4:5], v2, off176; GFX1250-FAKE16-NEXT: s_endpgm177;178; GFX1250-GISEL-LABEL: test_cvt_sr_fp8_f32_byte1_dpp:179; GFX1250-GISEL: ; %bb.0:180; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1181; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4182; GFX1250-GISEL-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:1 clamp quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1183; GFX1250-GISEL-NEXT: global_store_b32 v[6:7], v2, off184; GFX1250-GISEL-NEXT: s_endpgm185 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %a, i32 228, i32 15, i32 15, i1 1)186 %tmp1 = bitcast i32 %tmp0 to float187 %ret = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f32.e5m3(float %tmp1, i32 %r, i32 %old, i32 1)188 store i32 %ret, ptr addrspace(1) %out189 ret void190}191 192define float @test_cvt_f32_fp8_e5m3_byte0(i32 %a) {193; GFX1250-LABEL: test_cvt_f32_fp8_e5m3_byte0:194; GFX1250: ; %bb.0:195; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0196; GFX1250-NEXT: s_wait_kmcnt 0x0197; GFX1250-NEXT: v_cvt_f32_fp8_e64 v0, v0 clamp198; GFX1250-NEXT: s_set_pc_i64 s[30:31]199 %ret = tail call float @llvm.amdgcn.cvt.f32.fp8.e5m3(i32 %a, i32 0)200 ret float %ret201}202 203define float @test_cvt_f32_fp8_e5m3_byte1(i32 %a) {204; GFX1250-LABEL: test_cvt_f32_fp8_e5m3_byte1:205; GFX1250: ; %bb.0:206; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0207; GFX1250-NEXT: s_wait_kmcnt 0x0208; GFX1250-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:1 clamp209; GFX1250-NEXT: s_set_pc_i64 s[30:31]210 %ret = tail call float @llvm.amdgcn.cvt.f32.fp8.e5m3(i32 %a, i32 1)211 ret float %ret212}213 214define float @test_cvt_f32_fp8_e5m3_byte2(i32 %a) {215; GFX1250-LABEL: test_cvt_f32_fp8_e5m3_byte2:216; GFX1250: ; %bb.0:217; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0218; GFX1250-NEXT: s_wait_kmcnt 0x0219; GFX1250-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:2 clamp220; GFX1250-NEXT: s_set_pc_i64 s[30:31]221 %ret = tail call float @llvm.amdgcn.cvt.f32.fp8.e5m3(i32 %a, i32 2)222 ret float %ret223}224 225define float @test_cvt_f32_fp8_e5m3_byte3(i32 %a) {226; GFX1250-LABEL: test_cvt_f32_fp8_e5m3_byte3:227; GFX1250: ; %bb.0:228; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0229; GFX1250-NEXT: s_wait_kmcnt 0x0230; GFX1250-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:3 clamp231; GFX1250-NEXT: s_set_pc_i64 s[30:31]232 %ret = tail call float @llvm.amdgcn.cvt.f32.fp8.e5m3(i32 %a, i32 3)233 ret float %ret234}235