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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG-REAL16 %s3; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG-FAKE16 %s4; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-REAL16 %s5; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-FAKE16 %s6 7declare i16 @llvm.amdgcn.cvt.pk.bf8.f16(<2 x half>)8declare i16 @llvm.amdgcn.cvt.pk.fp8.f16(<2 x half>)9declare i32 @llvm.amdgcn.cvt.sr.bf8.f16(half, i32, i32, i32)10declare i32 @llvm.amdgcn.cvt.sr.fp8.f16(half, i32, i32, i32)11 12define amdgpu_ps void @test_cvt_pk_bf8_f16_v(<2 x half> %a, ptr addrspace(1) %out) {13; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_bf8_f16_v:14; GFX1250-SDAG-REAL16: ; %bb.0:15; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 116; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v117; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_bf8_f16 v0.l, v018; GFX1250-SDAG-REAL16-NEXT: global_store_b16 v[2:3], v0, off19; GFX1250-SDAG-REAL16-NEXT: s_endpgm20;21; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_bf8_f16_v:22; GFX1250-SDAG-FAKE16: ; %bb.0:23; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 124; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v125; GFX1250-SDAG-FAKE16-NEXT: v_cvt_pk_bf8_f16 v0, v026; GFX1250-SDAG-FAKE16-NEXT: global_store_b16 v[2:3], v0, off27; GFX1250-SDAG-FAKE16-NEXT: s_endpgm28;29; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_bf8_f16_v:30; GFX1250-GISEL-REAL16: ; %bb.0:31; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 132; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v233; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_bf8_f16 v0.l, v034; GFX1250-GISEL-REAL16-NEXT: global_store_b16 v[4:5], v0, off35; GFX1250-GISEL-REAL16-NEXT: s_endpgm36;37; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_bf8_f16_v:38; GFX1250-GISEL-FAKE16: ; %bb.0:39; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 140; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v241; GFX1250-GISEL-FAKE16-NEXT: v_cvt_pk_bf8_f16 v0, v042; GFX1250-GISEL-FAKE16-NEXT: global_store_b16 v[4:5], v0, off43; GFX1250-GISEL-FAKE16-NEXT: s_endpgm44 %cvt = tail call i16 @llvm.amdgcn.cvt.pk.bf8.f16(<2 x half> %a)45 store i16 %cvt, ptr addrspace(1) %out46 ret void47}48 49define amdgpu_ps void @test_cvt_pk_bf8_f16_s(<2 x half> inreg %a, ptr addrspace(1) %out) {50; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_bf8_f16_s:51; GFX1250-SDAG-REAL16: ; %bb.0:52; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 153; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_bf8_f16 v2.l, s054; GFX1250-SDAG-REAL16-NEXT: global_store_b16 v[0:1], v2, off55; GFX1250-SDAG-REAL16-NEXT: s_endpgm56;57; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_bf8_f16_s:58; GFX1250-SDAG-FAKE16: ; %bb.0:59; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 160; GFX1250-SDAG-FAKE16-NEXT: v_cvt_pk_bf8_f16 v2, s061; GFX1250-SDAG-FAKE16-NEXT: global_store_b16 v[0:1], v2, off62; GFX1250-SDAG-FAKE16-NEXT: s_endpgm63;64; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_bf8_f16_s:65; GFX1250-GISEL-REAL16: ; %bb.0:66; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 167; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_bf8_f16 v2.l, s068; GFX1250-GISEL-REAL16-NEXT: global_store_b16 v[0:1], v2, off69; GFX1250-GISEL-REAL16-NEXT: s_endpgm70;71; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_bf8_f16_s:72; GFX1250-GISEL-FAKE16: ; %bb.0:73; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 174; GFX1250-GISEL-FAKE16-NEXT: v_cvt_pk_bf8_f16 v2, s075; GFX1250-GISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off76; GFX1250-GISEL-FAKE16-NEXT: s_endpgm77 %cvt = tail call i16 @llvm.amdgcn.cvt.pk.bf8.f16(<2 x half> %a)78 store i16 %cvt, ptr addrspace(1) %out79 ret void80}81 82define amdgpu_ps void @test_cvt_pk_bf8_f16_l(ptr addrspace(1) %out) {83; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_bf8_f16_l:84; GFX1250-SDAG-REAL16: ; %bb.0:85; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 186; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_bf8_f16 v2.l, 0x5640000087; GFX1250-SDAG-REAL16-NEXT: global_store_b16 v[0:1], v2, off88; GFX1250-SDAG-REAL16-NEXT: s_endpgm89;90; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_bf8_f16_l:91; GFX1250-SDAG-FAKE16: ; %bb.0:92; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 193; GFX1250-SDAG-FAKE16-NEXT: v_cvt_pk_bf8_f16 v2, 0x5640000094; GFX1250-SDAG-FAKE16-NEXT: global_store_b16 v[0:1], v2, off95; GFX1250-SDAG-FAKE16-NEXT: s_endpgm96;97; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_bf8_f16_l:98; GFX1250-GISEL-REAL16: ; %bb.0:99; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1100; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_bf8_f16 v2.l, 0x56400000101; GFX1250-GISEL-REAL16-NEXT: global_store_b16 v[0:1], v2, off102; GFX1250-GISEL-REAL16-NEXT: s_endpgm103;104; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_bf8_f16_l:105; GFX1250-GISEL-FAKE16: ; %bb.0:106; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1107; GFX1250-GISEL-FAKE16-NEXT: v_cvt_pk_bf8_f16 v2, 0x56400000108; GFX1250-GISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off109; GFX1250-GISEL-FAKE16-NEXT: s_endpgm110 %cvt = tail call i16 @llvm.amdgcn.cvt.pk.bf8.f16(<2 x half> <half 0.0, half 100.0>)111 store i16 %cvt, ptr addrspace(1) %out112 ret void113}114 115define amdgpu_ps void @test_cvt_pk_fp8_f16_v(<2 x half> %a, ptr addrspace(1) %out) {116; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_fp8_f16_v:117; GFX1250-SDAG-REAL16: ; %bb.0:118; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1119; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1120; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_fp8_f16 v0.l, v0121; GFX1250-SDAG-REAL16-NEXT: global_store_b16 v[2:3], v0, off122; GFX1250-SDAG-REAL16-NEXT: s_endpgm123;124; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_fp8_f16_v:125; GFX1250-SDAG-FAKE16: ; %bb.0:126; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1127; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1128; GFX1250-SDAG-FAKE16-NEXT: v_cvt_pk_fp8_f16 v0, v0129; GFX1250-SDAG-FAKE16-NEXT: global_store_b16 v[2:3], v0, off130; GFX1250-SDAG-FAKE16-NEXT: s_endpgm131;132; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_fp8_f16_v:133; GFX1250-GISEL-REAL16: ; %bb.0:134; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1135; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2136; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_fp8_f16 v0.l, v0137; GFX1250-GISEL-REAL16-NEXT: global_store_b16 v[4:5], v0, off138; GFX1250-GISEL-REAL16-NEXT: s_endpgm139;140; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_fp8_f16_v:141; GFX1250-GISEL-FAKE16: ; %bb.0:142; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1143; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2144; GFX1250-GISEL-FAKE16-NEXT: v_cvt_pk_fp8_f16 v0, v0145; GFX1250-GISEL-FAKE16-NEXT: global_store_b16 v[4:5], v0, off146; GFX1250-GISEL-FAKE16-NEXT: s_endpgm147 %cvt = tail call i16 @llvm.amdgcn.cvt.pk.fp8.f16(<2 x half> %a)148 store i16 %cvt, ptr addrspace(1) %out149 ret void150}151 152define amdgpu_ps void @test_cvt_pk_fp8_f16_s(<2 x half> inreg %a, ptr addrspace(1) %out) {153; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_fp8_f16_s:154; GFX1250-SDAG-REAL16: ; %bb.0:155; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1156; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_fp8_f16 v2.l, s0157; GFX1250-SDAG-REAL16-NEXT: global_store_b16 v[0:1], v2, off158; GFX1250-SDAG-REAL16-NEXT: s_endpgm159;160; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_fp8_f16_s:161; GFX1250-SDAG-FAKE16: ; %bb.0:162; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1163; GFX1250-SDAG-FAKE16-NEXT: v_cvt_pk_fp8_f16 v2, s0164; GFX1250-SDAG-FAKE16-NEXT: global_store_b16 v[0:1], v2, off165; GFX1250-SDAG-FAKE16-NEXT: s_endpgm166;167; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_fp8_f16_s:168; GFX1250-GISEL-REAL16: ; %bb.0:169; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1170; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_fp8_f16 v2.l, s0171; GFX1250-GISEL-REAL16-NEXT: global_store_b16 v[0:1], v2, off172; GFX1250-GISEL-REAL16-NEXT: s_endpgm173;174; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_fp8_f16_s:175; GFX1250-GISEL-FAKE16: ; %bb.0:176; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1177; GFX1250-GISEL-FAKE16-NEXT: v_cvt_pk_fp8_f16 v2, s0178; GFX1250-GISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off179; GFX1250-GISEL-FAKE16-NEXT: s_endpgm180 %cvt = tail call i16 @llvm.amdgcn.cvt.pk.fp8.f16(<2 x half> %a)181 store i16 %cvt, ptr addrspace(1) %out182 ret void183}184 185define amdgpu_ps void @test_cvt_pk_fp8_f16_l(ptr addrspace(1) %out) {186; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_fp8_f16_l:187; GFX1250-SDAG-REAL16: ; %bb.0:188; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1189; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_fp8_f16 v2.l, 0x56400000190; GFX1250-SDAG-REAL16-NEXT: global_store_b16 v[0:1], v2, off191; GFX1250-SDAG-REAL16-NEXT: s_endpgm192;193; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_fp8_f16_l:194; GFX1250-SDAG-FAKE16: ; %bb.0:195; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1196; GFX1250-SDAG-FAKE16-NEXT: v_cvt_pk_fp8_f16 v2, 0x56400000197; GFX1250-SDAG-FAKE16-NEXT: global_store_b16 v[0:1], v2, off198; GFX1250-SDAG-FAKE16-NEXT: s_endpgm199;200; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_fp8_f16_l:201; GFX1250-GISEL-REAL16: ; %bb.0:202; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1203; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_fp8_f16 v2.l, 0x56400000204; GFX1250-GISEL-REAL16-NEXT: global_store_b16 v[0:1], v2, off205; GFX1250-GISEL-REAL16-NEXT: s_endpgm206;207; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_fp8_f16_l:208; GFX1250-GISEL-FAKE16: ; %bb.0:209; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1210; GFX1250-GISEL-FAKE16-NEXT: v_cvt_pk_fp8_f16 v2, 0x56400000211; GFX1250-GISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off212; GFX1250-GISEL-FAKE16-NEXT: s_endpgm213 %cvt = tail call i16 @llvm.amdgcn.cvt.pk.fp8.f16(<2 x half> <half 0.0, half 100.0>)214 store i16 %cvt, ptr addrspace(1) %out215 ret void216}217 218define amdgpu_ps void @test_cvt_sr_bf8_f16_byte0(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {219; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_bf8_f16_byte0:220; GFX1250-SDAG-REAL16: ; %bb.0:221; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1222; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3223; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.l, v1224; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off225; GFX1250-SDAG-REAL16-NEXT: s_endpgm226;227; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte0:228; GFX1250-SDAG-FAKE16: ; %bb.0:229; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1230; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3231; GFX1250-SDAG-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1232; GFX1250-SDAG-FAKE16-NEXT: global_store_b32 v[4:5], v2, off233; GFX1250-SDAG-FAKE16-NEXT: s_endpgm234;235; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_bf8_f16_byte0:236; GFX1250-GISEL-REAL16: ; %bb.0:237; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1238; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4239; GFX1250-GISEL-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.l, v1240; GFX1250-GISEL-REAL16-NEXT: global_store_b32 v[6:7], v2, off241; GFX1250-GISEL-REAL16-NEXT: s_endpgm242;243; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte0:244; GFX1250-GISEL-FAKE16: ; %bb.0:245; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1246; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4247; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1248; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off249; GFX1250-GISEL-FAKE16-NEXT: s_endpgm250 %cvt = tail call i32 @llvm.amdgcn.cvt.sr.bf8.f16(half %a, i32 %sr, i32 %old, i32 0)251 store i32 %cvt, ptr addrspace(1) %out252 ret void253}254 255define amdgpu_ps void @test_cvt_sr_bf8_f16_byte1(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {256; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_bf8_f16_byte1:257; GFX1250-SDAG-REAL16: ; %bb.0:258; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1259; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3260; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.l, v1 byte_sel:1261; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off262; GFX1250-SDAG-REAL16-NEXT: s_endpgm263;264; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte1:265; GFX1250-SDAG-FAKE16: ; %bb.0:266; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1267; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3268; GFX1250-SDAG-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:1269; GFX1250-SDAG-FAKE16-NEXT: global_store_b32 v[4:5], v2, off270; GFX1250-SDAG-FAKE16-NEXT: s_endpgm271;272; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_bf8_f16_byte1:273; GFX1250-GISEL-REAL16: ; %bb.0:274; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1275; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4276; GFX1250-GISEL-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.l, v1 byte_sel:1277; GFX1250-GISEL-REAL16-NEXT: global_store_b32 v[6:7], v2, off278; GFX1250-GISEL-REAL16-NEXT: s_endpgm279;280; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte1:281; GFX1250-GISEL-FAKE16: ; %bb.0:282; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1283; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4284; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:1285; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off286; GFX1250-GISEL-FAKE16-NEXT: s_endpgm287 %cvt = tail call i32 @llvm.amdgcn.cvt.sr.bf8.f16(half %a, i32 %sr, i32 %old, i32 1)288 store i32 %cvt, ptr addrspace(1) %out289 ret void290}291 292define amdgpu_ps void @test_cvt_sr_bf8_f16_byte2(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {293; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_bf8_f16_byte2:294; GFX1250-SDAG-REAL16: ; %bb.0:295; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1296; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3297; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.l, v1 byte_sel:2298; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off299; GFX1250-SDAG-REAL16-NEXT: s_endpgm300;301; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte2:302; GFX1250-SDAG-FAKE16: ; %bb.0:303; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1304; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3305; GFX1250-SDAG-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:2306; GFX1250-SDAG-FAKE16-NEXT: global_store_b32 v[4:5], v2, off307; GFX1250-SDAG-FAKE16-NEXT: s_endpgm308;309; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_bf8_f16_byte2:310; GFX1250-GISEL-REAL16: ; %bb.0:311; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1312; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4313; GFX1250-GISEL-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.l, v1 byte_sel:2314; GFX1250-GISEL-REAL16-NEXT: global_store_b32 v[6:7], v2, off315; GFX1250-GISEL-REAL16-NEXT: s_endpgm316;317; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte2:318; GFX1250-GISEL-FAKE16: ; %bb.0:319; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1320; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4321; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:2322; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off323; GFX1250-GISEL-FAKE16-NEXT: s_endpgm324 %cvt = tail call i32 @llvm.amdgcn.cvt.sr.bf8.f16(half %a, i32 %sr, i32 %old, i32 2)325 store i32 %cvt, ptr addrspace(1) %out326 ret void327}328 329define amdgpu_ps void @test_cvt_sr_bf8_f16_byte3(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {330; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_bf8_f16_byte3:331; GFX1250-SDAG-REAL16: ; %bb.0:332; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1333; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3334; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.l, v1 byte_sel:3335; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off336; GFX1250-SDAG-REAL16-NEXT: s_endpgm337;338; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte3:339; GFX1250-SDAG-FAKE16: ; %bb.0:340; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1341; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3342; GFX1250-SDAG-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:3343; GFX1250-SDAG-FAKE16-NEXT: global_store_b32 v[4:5], v2, off344; GFX1250-SDAG-FAKE16-NEXT: s_endpgm345;346; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_bf8_f16_byte3:347; GFX1250-GISEL-REAL16: ; %bb.0:348; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1349; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4350; GFX1250-GISEL-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.l, v1 byte_sel:3351; GFX1250-GISEL-REAL16-NEXT: global_store_b32 v[6:7], v2, off352; GFX1250-GISEL-REAL16-NEXT: s_endpgm353;354; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte3:355; GFX1250-GISEL-FAKE16: ; %bb.0:356; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1357; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4358; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:3359; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off360; GFX1250-GISEL-FAKE16-NEXT: s_endpgm361 %cvt = tail call i32 @llvm.amdgcn.cvt.sr.bf8.f16(half %a, i32 %sr, i32 %old, i32 3)362 store i32 %cvt, ptr addrspace(1) %out363 ret void364}365 366define amdgpu_ps void @test_cvt_sr_bf8_f16_hi_byte0(<2 x half> %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {367; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_bf8_f16_hi_byte0:368; GFX1250-SDAG-REAL16: ; %bb.0:369; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1370; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3371; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.h, v1372; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off373; GFX1250-SDAG-REAL16-NEXT: s_endpgm374;375; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_bf8_f16_hi_byte0:376; GFX1250-SDAG-FAKE16: ; %bb.0:377; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1378; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_lshrrev_b32 v0, 16, v0379; GFX1250-SDAG-FAKE16-NEXT: v_mov_b32_e32 v4, v3380; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)381; GFX1250-SDAG-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1382; GFX1250-SDAG-FAKE16-NEXT: global_store_b32 v[4:5], v2, off383; GFX1250-SDAG-FAKE16-NEXT: s_endpgm384;385; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_bf8_f16_hi_byte0:386; GFX1250-GISEL-REAL16: ; %bb.0:387; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1388; GFX1250-GISEL-REAL16-NEXT: v_dual_lshrrev_b32 v0, 16, v0 :: v_dual_mov_b32 v6, v3389; GFX1250-GISEL-REAL16-NEXT: v_mov_b32_e32 v7, v4390; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2)391; GFX1250-GISEL-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.l, v1392; GFX1250-GISEL-REAL16-NEXT: global_store_b32 v[6:7], v2, off393; GFX1250-GISEL-REAL16-NEXT: s_endpgm394;395; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_bf8_f16_hi_byte0:396; GFX1250-GISEL-FAKE16: ; %bb.0:397; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1398; GFX1250-GISEL-FAKE16-NEXT: v_dual_lshrrev_b32 v0, 16, v0 :: v_dual_mov_b32 v6, v3399; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v7, v4400; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)401; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1402; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off403; GFX1250-GISEL-FAKE16-NEXT: s_endpgm404 %a.1 = extractelement <2 x half> %a, i32 1405 %cvt = tail call i32 @llvm.amdgcn.cvt.sr.bf8.f16(half %a.1, i32 %sr, i32 %old, i32 0)406 store i32 %cvt, ptr addrspace(1) %out407 ret void408}409 410define amdgpu_ps void @test_cvt_sr_fp8_f16_byte0(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {411; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_fp8_f16_byte0:412; GFX1250-SDAG-REAL16: ; %bb.0:413; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1414; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3415; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.l, v1416; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off417; GFX1250-SDAG-REAL16-NEXT: s_endpgm418;419; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte0:420; GFX1250-SDAG-FAKE16: ; %bb.0:421; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1422; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3423; GFX1250-SDAG-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1424; GFX1250-SDAG-FAKE16-NEXT: global_store_b32 v[4:5], v2, off425; GFX1250-SDAG-FAKE16-NEXT: s_endpgm426;427; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_fp8_f16_byte0:428; GFX1250-GISEL-REAL16: ; %bb.0:429; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1430; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4431; GFX1250-GISEL-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.l, v1432; GFX1250-GISEL-REAL16-NEXT: global_store_b32 v[6:7], v2, off433; GFX1250-GISEL-REAL16-NEXT: s_endpgm434;435; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte0:436; GFX1250-GISEL-FAKE16: ; %bb.0:437; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1438; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4439; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1440; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off441; GFX1250-GISEL-FAKE16-NEXT: s_endpgm442 %cvt = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f16(half %a, i32 %sr, i32 %old, i32 0)443 store i32 %cvt, ptr addrspace(1) %out444 ret void445}446 447define amdgpu_ps void @test_cvt_sr_fp8_f16_byte1(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {448; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_fp8_f16_byte1:449; GFX1250-SDAG-REAL16: ; %bb.0:450; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1451; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3452; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.l, v1 byte_sel:1453; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off454; GFX1250-SDAG-REAL16-NEXT: s_endpgm455;456; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte1:457; GFX1250-SDAG-FAKE16: ; %bb.0:458; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1459; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3460; GFX1250-SDAG-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:1461; GFX1250-SDAG-FAKE16-NEXT: global_store_b32 v[4:5], v2, off462; GFX1250-SDAG-FAKE16-NEXT: s_endpgm463;464; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_fp8_f16_byte1:465; GFX1250-GISEL-REAL16: ; %bb.0:466; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1467; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4468; GFX1250-GISEL-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.l, v1 byte_sel:1469; GFX1250-GISEL-REAL16-NEXT: global_store_b32 v[6:7], v2, off470; GFX1250-GISEL-REAL16-NEXT: s_endpgm471;472; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte1:473; GFX1250-GISEL-FAKE16: ; %bb.0:474; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1475; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4476; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:1477; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off478; GFX1250-GISEL-FAKE16-NEXT: s_endpgm479 %cvt = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f16(half %a, i32 %sr, i32 %old, i32 1)480 store i32 %cvt, ptr addrspace(1) %out481 ret void482}483 484define amdgpu_ps void @test_cvt_sr_fp8_f16_byte2(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {485; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_fp8_f16_byte2:486; GFX1250-SDAG-REAL16: ; %bb.0:487; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1488; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3489; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.l, v1 byte_sel:2490; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off491; GFX1250-SDAG-REAL16-NEXT: s_endpgm492;493; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte2:494; GFX1250-SDAG-FAKE16: ; %bb.0:495; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1496; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3497; GFX1250-SDAG-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:2498; GFX1250-SDAG-FAKE16-NEXT: global_store_b32 v[4:5], v2, off499; GFX1250-SDAG-FAKE16-NEXT: s_endpgm500;501; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_fp8_f16_byte2:502; GFX1250-GISEL-REAL16: ; %bb.0:503; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1504; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4505; GFX1250-GISEL-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.l, v1 byte_sel:2506; GFX1250-GISEL-REAL16-NEXT: global_store_b32 v[6:7], v2, off507; GFX1250-GISEL-REAL16-NEXT: s_endpgm508;509; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte2:510; GFX1250-GISEL-FAKE16: ; %bb.0:511; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1512; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4513; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:2514; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off515; GFX1250-GISEL-FAKE16-NEXT: s_endpgm516 %cvt = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f16(half %a, i32 %sr, i32 %old, i32 2)517 store i32 %cvt, ptr addrspace(1) %out518 ret void519}520 521define amdgpu_ps void @test_cvt_sr_fp8_f16_byte3(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {522; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_fp8_f16_byte3:523; GFX1250-SDAG-REAL16: ; %bb.0:524; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1525; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3526; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.l, v1 byte_sel:3527; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off528; GFX1250-SDAG-REAL16-NEXT: s_endpgm529;530; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte3:531; GFX1250-SDAG-FAKE16: ; %bb.0:532; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1533; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3534; GFX1250-SDAG-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:3535; GFX1250-SDAG-FAKE16-NEXT: global_store_b32 v[4:5], v2, off536; GFX1250-SDAG-FAKE16-NEXT: s_endpgm537;538; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_fp8_f16_byte3:539; GFX1250-GISEL-REAL16: ; %bb.0:540; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1541; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4542; GFX1250-GISEL-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.l, v1 byte_sel:3543; GFX1250-GISEL-REAL16-NEXT: global_store_b32 v[6:7], v2, off544; GFX1250-GISEL-REAL16-NEXT: s_endpgm545;546; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte3:547; GFX1250-GISEL-FAKE16: ; %bb.0:548; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1549; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4550; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:3551; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off552; GFX1250-GISEL-FAKE16-NEXT: s_endpgm553 %cvt = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f16(half %a, i32 %sr, i32 %old, i32 3)554 store i32 %cvt, ptr addrspace(1) %out555 ret void556}557 558define amdgpu_ps void @test_cvt_sr_fp8_f16_hi_byte0(<2 x half> %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {559; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_fp8_f16_hi_byte0:560; GFX1250-SDAG-REAL16: ; %bb.0:561; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1562; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3563; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.h, v1564; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off565; GFX1250-SDAG-REAL16-NEXT: s_endpgm566;567; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_fp8_f16_hi_byte0:568; GFX1250-SDAG-FAKE16: ; %bb.0:569; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1570; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_lshrrev_b32 v0, 16, v0571; GFX1250-SDAG-FAKE16-NEXT: v_mov_b32_e32 v4, v3572; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)573; GFX1250-SDAG-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1574; GFX1250-SDAG-FAKE16-NEXT: global_store_b32 v[4:5], v2, off575; GFX1250-SDAG-FAKE16-NEXT: s_endpgm576;577; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_fp8_f16_hi_byte0:578; GFX1250-GISEL-REAL16: ; %bb.0:579; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1580; GFX1250-GISEL-REAL16-NEXT: v_dual_lshrrev_b32 v0, 16, v0 :: v_dual_mov_b32 v6, v3581; GFX1250-GISEL-REAL16-NEXT: v_mov_b32_e32 v7, v4582; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2)583; GFX1250-GISEL-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.l, v1584; GFX1250-GISEL-REAL16-NEXT: global_store_b32 v[6:7], v2, off585; GFX1250-GISEL-REAL16-NEXT: s_endpgm586;587; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_fp8_f16_hi_byte0:588; GFX1250-GISEL-FAKE16: ; %bb.0:589; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1590; GFX1250-GISEL-FAKE16-NEXT: v_dual_lshrrev_b32 v0, 16, v0 :: v_dual_mov_b32 v6, v3591; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v7, v4592; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)593; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1594; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off595; GFX1250-GISEL-FAKE16-NEXT: s_endpgm596 %a.1 = extractelement <2 x half> %a, i32 1597 %cvt = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f16(half %a.1, i32 %sr, i32 %old, i32 0)598 store i32 %cvt, ptr addrspace(1) %out599 ret void600}601 602;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:603; GFX1250: {{.*}}604