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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GCN %s3; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GCN %s4 5declare <2 x half> @llvm.amdgcn.cvt.sr.pk.f16.f32(float, float, i32) #06 7define amdgpu_ps float @cvt_sr_pk_f16_f32_vvv(float %src0, float %src1, i32 %src2) #1 {8; GCN-LABEL: cvt_sr_pk_f16_f32_vvv:9; GCN: ; %bb.0:10; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 111; GCN-NEXT: v_cvt_sr_pk_f16_f32 v0, v0, v1, v212; GCN-NEXT: ; return to shader part epilog13 %cvt = call <2 x half> @llvm.amdgcn.cvt.sr.pk.f16.f32(float %src0, float %src1, i32 %src2) #014 %ret = bitcast <2 x half> %cvt to float15 ret float %ret16}17 18define amdgpu_ps float @cvt_sr_pk_f16_f32_sss(float inreg %src0, float inreg %src1, i32 inreg %src2) #1 {19; GCN-LABEL: cvt_sr_pk_f16_f32_sss:20; GCN: ; %bb.0:21; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 122; GCN-NEXT: v_mov_b32_e32 v0, s223; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)24; GCN-NEXT: v_cvt_sr_pk_f16_f32 v0, s0, s1, v025; GCN-NEXT: ; return to shader part epilog26 %cvt = call <2 x half> @llvm.amdgcn.cvt.sr.pk.f16.f32(float %src0, float %src1, i32 %src2) #027 %ret = bitcast <2 x half> %cvt to float28 ret float %ret29}30 31define amdgpu_ps float @cvt_sr_pk_f16_f32_vvi(float %src0, float %src1) #1 {32; GCN-LABEL: cvt_sr_pk_f16_f32_vvi:33; GCN: ; %bb.0:34; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 135; GCN-NEXT: v_cvt_sr_pk_f16_f32 v0, v0, v1, 0x1000236; GCN-NEXT: ; return to shader part epilog37 %cvt = call <2 x half> @llvm.amdgcn.cvt.sr.pk.f16.f32(float %src0, float %src1, i32 65538) #038 %ret = bitcast <2 x half> %cvt to float39 ret float %ret40}41 42define amdgpu_ps float @cvt_sr_pk_f16_f32_vvi_mods(float %src0, float %src1) #1 {43; GCN-LABEL: cvt_sr_pk_f16_f32_vvi_mods:44; GCN: ; %bb.0:45; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 146; GCN-NEXT: v_cvt_sr_pk_f16_f32 v0, -v0, |v1|, 147; GCN-NEXT: ; return to shader part epilog48 %s0 = fneg float %src049 %s1 = call float @llvm.fabs.f32(float %src1) #050 %cvt = call <2 x half> @llvm.amdgcn.cvt.sr.pk.f16.f32(float %s0, float %s1, i32 1) #051 %ret = bitcast <2 x half> %cvt to float52 ret float %ret53}54 55define amdgpu_ps float @cvt_sr_pk_f16_f32_ssi(float inreg %src0, float inreg %src1) #1 {56; GCN-LABEL: cvt_sr_pk_f16_f32_ssi:57; GCN: ; %bb.0:58; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 159; GCN-NEXT: v_cvt_sr_pk_f16_f32 v0, s0, s1, 160; GCN-NEXT: ; return to shader part epilog61 %cvt = call <2 x half> @llvm.amdgcn.cvt.sr.pk.f16.f32(float %src0, float %src1, i32 1) #062 %ret = bitcast <2 x half> %cvt to float63 ret float %ret64}65 66declare float @llvm.fabs.f32(float) #067 68attributes #0 = { nounwind readnone }69attributes #1 = { nounwind }70