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1; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s2; RUN: llc -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s3; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s5 6; GCN-LABEL: {{^}}s_cvt_pk_u16_u32:7; GCN-DAG: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s[4:5], 0x{{9|24}}8; GCN: v_mov_b32_e32 [[VY:v[0-9]+]], s[[#LOAD + 3]]9; SI: v_cvt_pk_u16_u32_e32 v{{[0-9]+}}, s[[#LOAD + 2]], [[VY]]10; VI: v_cvt_pk_u16_u32 v{{[0-9]+}}, s[[#LOAD + 2]], [[VY]]11define amdgpu_kernel void @s_cvt_pk_u16_u32(ptr addrspace(1) %out, i32 %x, i32 %y) #0 {12 %result = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %x, i32 %y)13 %r = bitcast <2 x i16> %result to i3214 store i32 %r, ptr addrspace(1) %out15 ret void16}17 18; GCN-LABEL: {{^}}s_cvt_pk_u16_samereg_i32:19; GCN: s_load_dword [[X:s[0-9]+]]20; GCN: v_cvt_pk_u16_u32{{(_e64)*}} v{{[0-9]+}}, [[X]], [[X]]21define amdgpu_kernel void @s_cvt_pk_u16_samereg_i32(ptr addrspace(1) %out, i32 %x) #0 {22 %result = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %x, i32 %x)23 %r = bitcast <2 x i16> %result to i3224 store i32 %r, ptr addrspace(1) %out25 ret void26}27 28; GCN-LABEL: {{^}}v_cvt_pk_u16_u32:29; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]30; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]31; SI: v_cvt_pk_u16_u32_e32 v{{[0-9]+}}, [[A]], [[B]]32; VI: v_cvt_pk_u16_u32 v{{[0-9]+}}, [[A]], [[B]]33define amdgpu_kernel void @v_cvt_pk_u16_u32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {34 %tid = call i32 @llvm.amdgcn.workitem.id.x()35 %tid.ext = sext i32 %tid to i6436 %a.gep = getelementptr inbounds i32, ptr addrspace(1) %a.ptr, i64 %tid.ext37 %b.gep = getelementptr inbounds i32, ptr addrspace(1) %b.ptr, i64 %tid.ext38 %out.gep = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %tid.ext39 %a = load volatile i32, ptr addrspace(1) %a.gep40 %b = load volatile i32, ptr addrspace(1) %b.gep41 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %a, i32 %b)42 %r = bitcast <2 x i16> %cvt to i3243 store i32 %r, ptr addrspace(1) %out.gep44 ret void45}46 47; GCN-LABEL: {{^}}v_cvt_pk_u16_u32_reg_imm:48; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]49; GCN: v_cvt_pk_u16_u32{{(_e64)*}} v{{[0-9]+}}, [[A]], 150define amdgpu_kernel void @v_cvt_pk_u16_u32_reg_imm(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {51 %tid = call i32 @llvm.amdgcn.workitem.id.x()52 %tid.ext = sext i32 %tid to i6453 %a.gep = getelementptr inbounds i32, ptr addrspace(1) %a.ptr, i64 %tid.ext54 %out.gep = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %tid.ext55 %a = load volatile i32, ptr addrspace(1) %a.gep56 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %a, i32 1)57 %r = bitcast <2 x i16> %cvt to i3258 store i32 %r, ptr addrspace(1) %out.gep59 ret void60}61 62; GCN-LABEL: {{^}}v_cvt_pk_u16_u32_imm_reg:63; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]64; SI: v_cvt_pk_u16_u32_e32 v{{[0-9]+}}, 1, [[A]]65; VI: v_cvt_pk_u16_u32 v{{[0-9]+}}, 1, [[A]]66define amdgpu_kernel void @v_cvt_pk_u16_u32_imm_reg(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {67 %tid = call i32 @llvm.amdgcn.workitem.id.x()68 %tid.ext = sext i32 %tid to i6469 %a.gep = getelementptr inbounds i32, ptr addrspace(1) %a.ptr, i64 %tid.ext70 %out.gep = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %tid.ext71 %a = load volatile i32, ptr addrspace(1) %a.gep72 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 1, i32 %a)73 %r = bitcast <2 x i16> %cvt to i3274 store i32 %r, ptr addrspace(1) %out.gep75 ret void76}77 78declare <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32, i32) #179declare i32 @llvm.amdgcn.workitem.id.x() #180 81 82attributes #0 = { nounwind }83attributes #1 = { nounwind readnone }84