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1; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s2; RUN: llc -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s3; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s5 6; GCN-LABEL: {{^}}s_cvt_pknorm_i16_f32:7; GCN-DAG: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s[4:5], 0x{{9|24}}8; GCN: v_mov_b32_e32 [[VY:v[0-9]+]], s[[#LOAD + 3]]9; SI: v_cvt_pknorm_i16_f32_e32 v{{[0-9]+}}, s[[#LOAD + 2]], [[VY]]10; VI: v_cvt_pknorm_i16_f32 v{{[0-9]+}}, s[[#LOAD + 2]], [[VY]]11define amdgpu_kernel void @s_cvt_pknorm_i16_f32(ptr addrspace(1) %out, float %x, float %y) #0 {12 %result = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %x, float %y)13 %r = bitcast <2 x i16> %result to i3214 store i32 %r, ptr addrspace(1) %out15 ret void16}17 18; GCN-LABEL: {{^}}s_cvt_pknorm_i16_samereg_f32:19; GCN: s_load_dword [[X:s[0-9]+]]20; GCN: v_cvt_pknorm_i16_f32{{(_e64)*}} v{{[0-9]+}}, [[X]], [[X]]21define amdgpu_kernel void @s_cvt_pknorm_i16_samereg_f32(ptr addrspace(1) %out, float %x) #0 {22 %result = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %x, float %x)23 %r = bitcast <2 x i16> %result to i3224 store i32 %r, ptr addrspace(1) %out25 ret void26}27 28; GCN-LABEL: {{^}}v_cvt_pknorm_i16_f32:29; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]30; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]31; SI: v_cvt_pknorm_i16_f32_e32 v{{[0-9]+}}, [[A]], [[B]]32; VI: v_cvt_pknorm_i16_f32 v{{[0-9]+}}, [[A]], [[B]]33define amdgpu_kernel void @v_cvt_pknorm_i16_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {34 %tid = call i32 @llvm.amdgcn.workitem.id.x()35 %tid.ext = sext i32 %tid to i6436 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext37 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext38 %out.gep = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %tid.ext39 %a = load volatile float, ptr addrspace(1) %a.gep40 %b = load volatile float, ptr addrspace(1) %b.gep41 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %a, float %b)42 %r = bitcast <2 x i16> %cvt to i3243 store i32 %r, ptr addrspace(1) %out.gep44 ret void45}46 47; GCN-LABEL: {{^}}v_cvt_pknorm_i16_f32_reg_imm:48; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]49; GCN: v_cvt_pknorm_i16_f32{{(_e64)*}} v{{[0-9]+}}, [[A]], 1.050define amdgpu_kernel void @v_cvt_pknorm_i16_f32_reg_imm(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {51 %tid = call i32 @llvm.amdgcn.workitem.id.x()52 %tid.ext = sext i32 %tid to i6453 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext54 %out.gep = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %tid.ext55 %a = load volatile float, ptr addrspace(1) %a.gep56 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %a, float 1.0)57 %r = bitcast <2 x i16> %cvt to i3258 store i32 %r, ptr addrspace(1) %out.gep59 ret void60}61 62; GCN-LABEL: {{^}}v_cvt_pknorm_i16_f32_imm_reg:63; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]64; SI: v_cvt_pknorm_i16_f32_e32 v{{[0-9]+}}, 1.0, [[A]]65; VI: v_cvt_pknorm_i16_f32 v{{[0-9]+}}, 1.0, [[A]]66define amdgpu_kernel void @v_cvt_pknorm_i16_f32_imm_reg(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {67 %tid = call i32 @llvm.amdgcn.workitem.id.x()68 %tid.ext = sext i32 %tid to i6469 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext70 %out.gep = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %tid.ext71 %a = load volatile float, ptr addrspace(1) %a.gep72 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float 1.0, float %a)73 %r = bitcast <2 x i16> %cvt to i3274 store i32 %r, ptr addrspace(1) %out.gep75 ret void76}77 78; GCN-LABEL: {{^}}v_cvt_pknorm_i16_f32_fneg_lo:79; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]80; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]81; GCN: v_cvt_pknorm_i16_f32{{(_e64)*}} v{{[0-9]+}}, -[[A]], [[B]]82define amdgpu_kernel void @v_cvt_pknorm_i16_f32_fneg_lo(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {83 %tid = call i32 @llvm.amdgcn.workitem.id.x()84 %tid.ext = sext i32 %tid to i6485 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext86 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext87 %out.gep = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %tid.ext88 %a = load volatile float, ptr addrspace(1) %a.gep89 %b = load volatile float, ptr addrspace(1) %b.gep90 %neg.a = fsub float -0.0, %a91 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %neg.a, float %b)92 %r = bitcast <2 x i16> %cvt to i3293 store i32 %r, ptr addrspace(1) %out.gep94 ret void95}96 97; GCN-LABEL: {{^}}v_cvt_pknorm_i16_f32_fneg_hi:98; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]99; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]100; GCN: v_cvt_pknorm_i16_f32{{(_e64)*}} v{{[0-9]+}}, [[A]], -[[B]]101define amdgpu_kernel void @v_cvt_pknorm_i16_f32_fneg_hi(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {102 %tid = call i32 @llvm.amdgcn.workitem.id.x()103 %tid.ext = sext i32 %tid to i64104 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext105 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext106 %out.gep = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %tid.ext107 %a = load volatile float, ptr addrspace(1) %a.gep108 %b = load volatile float, ptr addrspace(1) %b.gep109 %neg.b = fsub float -0.0, %b110 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %a, float %neg.b)111 %r = bitcast <2 x i16> %cvt to i32112 store i32 %r, ptr addrspace(1) %out.gep113 ret void114}115 116; GCN-LABEL: {{^}}v_cvt_pknorm_i16_f32_fneg_lo_hi:117; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]118; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]119; GCN: v_cvt_pknorm_i16_f32{{(_e64)*}} v{{[0-9]+}}, -[[A]], -[[B]]120define amdgpu_kernel void @v_cvt_pknorm_i16_f32_fneg_lo_hi(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {121 %tid = call i32 @llvm.amdgcn.workitem.id.x()122 %tid.ext = sext i32 %tid to i64123 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext124 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext125 %out.gep = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %tid.ext126 %a = load volatile float, ptr addrspace(1) %a.gep127 %b = load volatile float, ptr addrspace(1) %b.gep128 %neg.a = fsub float -0.0, %a129 %neg.b = fsub float -0.0, %b130 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %neg.a, float %neg.b)131 %r = bitcast <2 x i16> %cvt to i32132 store i32 %r, ptr addrspace(1) %out.gep133 ret void134}135 136; GCN-LABEL: {{^}}v_cvt_pknorm_i16_f32_fneg_fabs_lo_fneg_hi:137; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]138; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]139; GCN: v_cvt_pknorm_i16_f32{{(_e64)*}} v{{[0-9]+}}, -|[[A]]|, -[[B]]140define amdgpu_kernel void @v_cvt_pknorm_i16_f32_fneg_fabs_lo_fneg_hi(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {141 %tid = call i32 @llvm.amdgcn.workitem.id.x()142 %tid.ext = sext i32 %tid to i64143 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext144 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext145 %out.gep = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %tid.ext146 %a = load volatile float, ptr addrspace(1) %a.gep147 %b = load volatile float, ptr addrspace(1) %b.gep148 %fabs.a = call float @llvm.fabs.f32(float %a)149 %neg.fabs.a = fsub float -0.0, %fabs.a150 %neg.b = fsub float -0.0, %b151 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %neg.fabs.a, float %neg.b)152 %r = bitcast <2 x i16> %cvt to i32153 store i32 %r, ptr addrspace(1) %out.gep154 ret void155}156 157declare <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float, float) #1158declare float @llvm.fabs.f32(float) #1159declare i32 @llvm.amdgcn.workitem.id.x() #1160 161 162attributes #0 = { nounwind }163attributes #1 = { nounwind readnone }164