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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s3; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s4 5declare <8 x half> @llvm.amdgcn.cvt.scale.pk8.f16.fp8(<2 x i32> %src, i32 %scale, i32 %scale_sel)6declare <8 x bfloat> @llvm.amdgcn.cvt.scale.pk8.bf16.fp8(<2 x i32> %src, i32 %scale, i32 %scale_sel)7declare <8 x half> @llvm.amdgcn.cvt.scale.pk8.f16.bf8(<2 x i32> %src, i32 %scale, i32 %scale_sel)8declare <8 x bfloat> @llvm.amdgcn.cvt.scale.pk8.bf16.bf8(<2 x i32> %src, i32 %scale, i32 %scale_sel)9declare <8 x half> @llvm.amdgcn.cvt.scale.pk8.f16.fp4(i32 %src, i32 %scale, i32 %scale_sel)10declare <8 x bfloat> @llvm.amdgcn.cvt.scale.pk8.bf16.fp4(i32 %src, i32 %scale, i32 %scale_sel)11declare <8 x float> @llvm.amdgcn.cvt.scale.pk8.f32.fp8(<2 x i32> %src, i32 %scale, i32 %scale_sel)12declare <8 x float> @llvm.amdgcn.cvt.scale.pk8.f32.bf8(<2 x i32> %src, i32 %scale, i32 %scale_sel)13declare <8 x float> @llvm.amdgcn.cvt.scale.pk8.f32.fp4(i32 %src, i32 %scale, i32 %scale_sel)14declare <16 x half> @llvm.amdgcn.cvt.scale.pk16.f16.fp6(<3 x i32> %src, i32 %scale, i32 %scale_sel)15declare <16 x bfloat> @llvm.amdgcn.cvt.scale.pk16.bf16.fp6(<3 x i32> %src, i32 %scale, i32 %scale_sel)16declare <16 x half> @llvm.amdgcn.cvt.scale.pk16.f16.bf6(<3 x i32> %src, i32 %scale, i32 %scale_sel)17declare <16 x bfloat> @llvm.amdgcn.cvt.scale.pk16.bf16.bf6(<3 x i32> %src, i32 %scale, i32 %scale_sel)18declare <16 x float> @llvm.amdgcn.cvt.scale.pk16.f32.fp6(<3 x i32> %src, i32 %scale, i32 %scale_sel)19declare <16 x float> @llvm.amdgcn.cvt.scale.pk16.f32.bf6(<3 x i32> %src, i32 %scale, i32 %scale_sel)20 21define amdgpu_ps void @test_cvt_scale_pk8_f16_fp8_vv(<2 x i32> %src, i32 %scale, ptr addrspace(1) %out) {22; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f16_fp8_vv:23; GFX1250-SDAG: ; %bb.0:24; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 125; GFX1250-SDAG-NEXT: v_dual_mov_b32 v9, v4 :: v_dual_mov_b32 v8, v326; GFX1250-SDAG-NEXT: v_cvt_scale_pk8_f16_fp8 v[4:7], v[0:1], v2 scale_sel:127; GFX1250-SDAG-NEXT: global_store_b128 v[8:9], v[4:7], off28; GFX1250-SDAG-NEXT: s_endpgm29;30; GFX1250-GISEL-LABEL: test_cvt_scale_pk8_f16_fp8_vv:31; GFX1250-GISEL: ; %bb.0:32; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 133; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v434; GFX1250-GISEL-NEXT: v_cvt_scale_pk8_f16_fp8 v[4:7], v[0:1], v2 scale_sel:135; GFX1250-GISEL-NEXT: global_store_b128 v[8:9], v[4:7], off36; GFX1250-GISEL-NEXT: s_endpgm37 %cvt = tail call <8 x half> @llvm.amdgcn.cvt.scale.pk8.f16.fp8(<2 x i32> %src, i32 %scale, i32 1)38 store <8 x half> %cvt, ptr addrspace(1) %out, align 839 ret void40}41 42define amdgpu_ps void @test_cvt_scale_pk8_f16_bf8_vv(<2 x i32> %src, i32 %scale, ptr addrspace(1) %out) {43; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f16_bf8_vv:44; GFX1250-SDAG: ; %bb.0:45; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 146; GFX1250-SDAG-NEXT: v_dual_mov_b32 v9, v4 :: v_dual_mov_b32 v8, v347; GFX1250-SDAG-NEXT: v_cvt_scale_pk8_f16_bf8 v[4:7], v[0:1], v248; GFX1250-SDAG-NEXT: global_store_b128 v[8:9], v[4:7], off49; GFX1250-SDAG-NEXT: s_endpgm50;51; GFX1250-GISEL-LABEL: test_cvt_scale_pk8_f16_bf8_vv:52; GFX1250-GISEL: ; %bb.0:53; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 154; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v455; GFX1250-GISEL-NEXT: v_cvt_scale_pk8_f16_bf8 v[4:7], v[0:1], v256; GFX1250-GISEL-NEXT: global_store_b128 v[8:9], v[4:7], off57; GFX1250-GISEL-NEXT: s_endpgm58 %cvt = tail call <8 x half> @llvm.amdgcn.cvt.scale.pk8.f16.bf8(<2 x i32> %src, i32 %scale, i32 0)59 store <8 x half> %cvt, ptr addrspace(1) %out, align 860 ret void61}62 63define amdgpu_ps void @test_cvt_scale_pk8_bf16_fp8_vv(<2 x i32> %src, i32 %scale, ptr addrspace(1) %out) {64; GFX1250-LABEL: test_cvt_scale_pk8_bf16_fp8_vv:65; GFX1250: ; %bb.0:66; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 167; GFX1250-NEXT: v_dual_mov_b32 v9, v4 :: v_dual_mov_b32 v8, v368; GFX1250-NEXT: v_cvt_scale_pk8_bf16_fp8 v[4:7], v[0:1], v2 scale_sel:169; GFX1250-NEXT: global_store_b128 v[8:9], v[4:7], off70; GFX1250-NEXT: s_endpgm71 %cvt = tail call <8 x bfloat> @llvm.amdgcn.cvt.scale.pk8.bf16.fp8(<2 x i32> %src, i32 %scale, i32 1)72 store <8 x bfloat> %cvt, ptr addrspace(1) %out, align 873 ret void74}75 76define amdgpu_ps void @test_cvt_scale_pk8_bf16_bf8_vv(<2 x i32> %src, i32 %scale, ptr addrspace(1) %out) {77; GFX1250-LABEL: test_cvt_scale_pk8_bf16_bf8_vv:78; GFX1250: ; %bb.0:79; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 180; GFX1250-NEXT: v_dual_mov_b32 v9, v4 :: v_dual_mov_b32 v8, v381; GFX1250-NEXT: v_cvt_scale_pk8_bf16_bf8 v[4:7], v[0:1], v2 scale_sel:282; GFX1250-NEXT: global_store_b128 v[8:9], v[4:7], off83; GFX1250-NEXT: s_endpgm84 %cvt = tail call <8 x bfloat> @llvm.amdgcn.cvt.scale.pk8.bf16.bf8(<2 x i32> %src, i32 %scale, i32 2)85 store <8 x bfloat> %cvt, ptr addrspace(1) %out, align 886 ret void87}88 89define amdgpu_ps void @test_cvt_scale_pk8_f16_fp4_vv(i32 %src, i32 %scale, ptr addrspace(1) %out) {90; GFX1250-LABEL: test_cvt_scale_pk8_f16_fp4_vv:91; GFX1250: ; %bb.0:92; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 193; GFX1250-NEXT: v_cvt_scale_pk8_f16_fp4 v[4:7], v0, v1 scale_sel:394; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off95; GFX1250-NEXT: s_endpgm96 %cvt = tail call <8 x half> @llvm.amdgcn.cvt.scale.pk8.f16.fp4(i32 %src, i32 %scale, i32 3)97 store <8 x half> %cvt, ptr addrspace(1) %out, align 1698 ret void99}100 101define amdgpu_ps void @test_cvt_scale_pk8_bf16_fp4_vv(i32 %src, i32 %scale, ptr addrspace(1) %out) {102; GFX1250-LABEL: test_cvt_scale_pk8_bf16_fp4_vv:103; GFX1250: ; %bb.0:104; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1105; GFX1250-NEXT: v_cvt_scale_pk8_bf16_fp4 v[4:7], v0, v1 scale_sel:4106; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off107; GFX1250-NEXT: s_endpgm108 %cvt = tail call <8 x bfloat> @llvm.amdgcn.cvt.scale.pk8.bf16.fp4(i32 %src, i32 %scale, i32 4)109 store <8 x bfloat> %cvt, ptr addrspace(1) %out, align 16110 ret void111}112 113define amdgpu_ps void @test_cvt_scale_pk8_f32_fp8_vv(<2 x i32> %src, i32 %scale, ptr addrspace(1) %out) {114; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f32_fp8_vv:115; GFX1250-SDAG: ; %bb.0:116; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1117; GFX1250-SDAG-NEXT: v_dual_mov_b32 v13, v4 :: v_dual_mov_b32 v12, v3118; GFX1250-SDAG-NEXT: v_cvt_scale_pk8_f32_fp8 v[4:11], v[0:1], v2 scale_sel:8119; GFX1250-SDAG-NEXT: s_clause 0x1120; GFX1250-SDAG-NEXT: global_store_b128 v[12:13], v[8:11], off offset:16121; GFX1250-SDAG-NEXT: global_store_b128 v[12:13], v[4:7], off122; GFX1250-SDAG-NEXT: s_endpgm123;124; GFX1250-GISEL-LABEL: test_cvt_scale_pk8_f32_fp8_vv:125; GFX1250-GISEL: ; %bb.0:126; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1127; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v13, v4128; GFX1250-GISEL-NEXT: v_cvt_scale_pk8_f32_fp8 v[4:11], v[0:1], v2 scale_sel:8129; GFX1250-GISEL-NEXT: s_clause 0x1130; GFX1250-GISEL-NEXT: global_store_b128 v[12:13], v[4:7], off131; GFX1250-GISEL-NEXT: global_store_b128 v[12:13], v[8:11], off offset:16132; GFX1250-GISEL-NEXT: s_endpgm133 %cvt = tail call <8 x float> @llvm.amdgcn.cvt.scale.pk8.f32.fp8(<2 x i32> %src, i32 %scale, i32 8)134 store <8 x float> %cvt, ptr addrspace(1) %out, align 16135 ret void136}137 138define amdgpu_ps void @test_cvt_scale_pk8_f32_bf8_vv(<2 x i32> %src, i32 %scale, ptr addrspace(1) %out) {139; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f32_bf8_vv:140; GFX1250-SDAG: ; %bb.0:141; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1142; GFX1250-SDAG-NEXT: v_dual_mov_b32 v13, v4 :: v_dual_mov_b32 v12, v3143; GFX1250-SDAG-NEXT: v_cvt_scale_pk8_f32_bf8 v[4:11], v[0:1], v2144; GFX1250-SDAG-NEXT: s_clause 0x1145; GFX1250-SDAG-NEXT: global_store_b128 v[12:13], v[8:11], off offset:16146; GFX1250-SDAG-NEXT: global_store_b128 v[12:13], v[4:7], off147; GFX1250-SDAG-NEXT: s_endpgm148;149; GFX1250-GISEL-LABEL: test_cvt_scale_pk8_f32_bf8_vv:150; GFX1250-GISEL: ; %bb.0:151; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1152; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v13, v4153; GFX1250-GISEL-NEXT: v_cvt_scale_pk8_f32_bf8 v[4:11], v[0:1], v2154; GFX1250-GISEL-NEXT: s_clause 0x1155; GFX1250-GISEL-NEXT: global_store_b128 v[12:13], v[4:7], off156; GFX1250-GISEL-NEXT: global_store_b128 v[12:13], v[8:11], off offset:16157; GFX1250-GISEL-NEXT: s_endpgm158 %cvt = tail call <8 x float> @llvm.amdgcn.cvt.scale.pk8.f32.bf8(<2 x i32> %src, i32 %scale, i32 0)159 store <8 x float> %cvt, ptr addrspace(1) %out, align 16160 ret void161}162 163define amdgpu_ps void @test_cvt_scale_pk8_f32_fp4_vv(i32 %src, i32 %scale, ptr addrspace(1) %out) {164; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f32_fp4_vv:165; GFX1250-SDAG: ; %bb.0:166; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1167; GFX1250-SDAG-NEXT: v_cvt_scale_pk8_f32_fp4 v[4:11], v0, v1 scale_sel:1168; GFX1250-SDAG-NEXT: s_clause 0x1169; GFX1250-SDAG-NEXT: global_store_b128 v[2:3], v[8:11], off offset:16170; GFX1250-SDAG-NEXT: global_store_b128 v[2:3], v[4:7], off171; GFX1250-SDAG-NEXT: s_endpgm172;173; GFX1250-GISEL-LABEL: test_cvt_scale_pk8_f32_fp4_vv:174; GFX1250-GISEL: ; %bb.0:175; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1176; GFX1250-GISEL-NEXT: v_cvt_scale_pk8_f32_fp4 v[4:11], v0, v1 scale_sel:1177; GFX1250-GISEL-NEXT: s_clause 0x1178; GFX1250-GISEL-NEXT: global_store_b128 v[2:3], v[4:7], off179; GFX1250-GISEL-NEXT: global_store_b128 v[2:3], v[8:11], off offset:16180; GFX1250-GISEL-NEXT: s_endpgm181 %cvt = tail call <8 x float> @llvm.amdgcn.cvt.scale.pk8.f32.fp4(i32 %src, i32 %scale, i32 1)182 store <8 x float> %cvt, ptr addrspace(1) %out, align 32183 ret void184}185 186define amdgpu_ps void @test_cvt_scale_pk16_f16_fp6_vv(<3 x i32> %src, i32 %scale, ptr addrspace(1) %out) {187; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f16_fp6_vv:188; GFX1250-SDAG: ; %bb.0:189; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1190; GFX1250-SDAG-NEXT: v_cvt_scale_pk16_f16_fp6 v[6:13], v[0:2], v3191; GFX1250-SDAG-NEXT: s_clause 0x1192; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16193; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[6:9], off194; GFX1250-SDAG-NEXT: s_endpgm195;196; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f16_fp6_vv:197; GFX1250-GISEL: ; %bb.0:198; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1199; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_fp6 v[6:13], v[0:2], v3200; GFX1250-GISEL-NEXT: s_clause 0x1201; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[6:9], off202; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16203; GFX1250-GISEL-NEXT: s_endpgm204 %cvt = tail call <16 x half> @llvm.amdgcn.cvt.scale.pk16.f16.fp6(<3 x i32> %src, i32 %scale, i32 0)205 store <16 x half> %cvt, ptr addrspace(1) %out, align 8206 ret void207}208 209define amdgpu_ps void @test_cvt_scale_pk16_f16_fp6_sl(<3 x i32> inreg %src, ptr addrspace(1) %out) {210; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f16_fp6_sl:211; GFX1250-SDAG: ; %bb.0:212; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1213; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v11, s1214; GFX1250-SDAG-NEXT: v_mov_b32_e32 v12, s2215; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)216; GFX1250-SDAG-NEXT: v_cvt_scale_pk16_f16_fp6 v[2:9], v[10:12], 0x64 scale_sel:1217; GFX1250-SDAG-NEXT: s_clause 0x1218; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16219; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off220; GFX1250-SDAG-NEXT: s_endpgm221;222; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f16_fp6_sl:223; GFX1250-GISEL: ; %bb.0:224; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1225; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v11, s1226; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, s0227; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)228; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_fp6 v[2:9], v[10:12], 0x64 scale_sel:1229; GFX1250-GISEL-NEXT: s_clause 0x1230; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off231; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16232; GFX1250-GISEL-NEXT: s_endpgm233 %cvt = tail call <16 x half> @llvm.amdgcn.cvt.scale.pk16.f16.fp6(<3 x i32> %src, i32 100, i32 1)234 store <16 x half> %cvt, ptr addrspace(1) %out, align 8235 ret void236}237 238define amdgpu_ps void @test_cvt_scale_pk16_bf16_fp6_vv(<3 x i32> %src, i32 %scale, ptr addrspace(1) %out) {239; GFX1250-LABEL: test_cvt_scale_pk16_bf16_fp6_vv:240; GFX1250: ; %bb.0:241; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1242; GFX1250-NEXT: v_cvt_scale_pk16_bf16_fp6 v[6:13], v[0:2], v3 scale_sel:2243; GFX1250-NEXT: s_clause 0x1244; GFX1250-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16245; GFX1250-NEXT: global_store_b128 v[4:5], v[6:9], off246; GFX1250-NEXT: s_endpgm247 %cvt = tail call <16 x bfloat> @llvm.amdgcn.cvt.scale.pk16.bf16.fp6(<3 x i32> %src, i32 %scale, i32 2)248 store <16 x bfloat> %cvt, ptr addrspace(1) %out, align 8249 ret void250}251 252define amdgpu_ps void @test_cvt_scale_pk16_bf16_fp6_sl(<3 x i32> inreg %src, ptr addrspace(1) %out) {253; GFX1250-LABEL: test_cvt_scale_pk16_bf16_fp6_sl:254; GFX1250: ; %bb.0:255; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1256; GFX1250-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v11, s1257; GFX1250-NEXT: v_mov_b32_e32 v12, s2258; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)259; GFX1250-NEXT: v_cvt_scale_pk16_bf16_fp6 v[2:9], v[10:12], 0x64 scale_sel:3260; GFX1250-NEXT: s_clause 0x1261; GFX1250-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16262; GFX1250-NEXT: global_store_b128 v[0:1], v[2:5], off263; GFX1250-NEXT: s_endpgm264 %cvt = tail call <16 x bfloat> @llvm.amdgcn.cvt.scale.pk16.bf16.fp6(<3 x i32> %src, i32 100, i32 3)265 store <16 x bfloat> %cvt, ptr addrspace(1) %out, align 8266 ret void267}268 269define amdgpu_ps void @test_cvt_scale_pk16_f16_bf6_vv(<3 x i32> %src, i32 %scale, ptr addrspace(1) %out) {270; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f16_bf6_vv:271; GFX1250-SDAG: ; %bb.0:272; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1273; GFX1250-SDAG-NEXT: v_cvt_scale_pk16_f16_bf6 v[6:13], v[0:2], v3 scale_sel:4274; GFX1250-SDAG-NEXT: s_clause 0x1275; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16276; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[6:9], off277; GFX1250-SDAG-NEXT: s_endpgm278;279; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f16_bf6_vv:280; GFX1250-GISEL: ; %bb.0:281; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1282; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_bf6 v[6:13], v[0:2], v3 scale_sel:4283; GFX1250-GISEL-NEXT: s_clause 0x1284; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[6:9], off285; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16286; GFX1250-GISEL-NEXT: s_endpgm287 %cvt = tail call <16 x half> @llvm.amdgcn.cvt.scale.pk16.f16.bf6(<3 x i32> %src, i32 %scale, i32 4)288 store <16 x half> %cvt, ptr addrspace(1) %out, align 8289 ret void290}291 292define amdgpu_ps void @test_cvt_scale_pk16_f16_bf6_sl(<3 x i32> inreg %src, ptr addrspace(1) %out) {293; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f16_bf6_sl:294; GFX1250-SDAG: ; %bb.0:295; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1296; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v11, s1297; GFX1250-SDAG-NEXT: v_mov_b32_e32 v12, s2298; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)299; GFX1250-SDAG-NEXT: v_cvt_scale_pk16_f16_bf6 v[2:9], v[10:12], 0x64 scale_sel:5300; GFX1250-SDAG-NEXT: s_clause 0x1301; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16302; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off303; GFX1250-SDAG-NEXT: s_endpgm304;305; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f16_bf6_sl:306; GFX1250-GISEL: ; %bb.0:307; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1308; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v11, s1309; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, s0310; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)311; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_bf6 v[2:9], v[10:12], 0x64 scale_sel:5312; GFX1250-GISEL-NEXT: s_clause 0x1313; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off314; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16315; GFX1250-GISEL-NEXT: s_endpgm316 %cvt = tail call <16 x half> @llvm.amdgcn.cvt.scale.pk16.f16.bf6(<3 x i32> %src, i32 100, i32 5)317 store <16 x half> %cvt, ptr addrspace(1) %out, align 8318 ret void319}320 321define amdgpu_ps void @test_cvt_scale_pk16_bf16_bf6_vv(<3 x i32> %src, i32 %scale, ptr addrspace(1) %out) {322; GFX1250-LABEL: test_cvt_scale_pk16_bf16_bf6_vv:323; GFX1250: ; %bb.0:324; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1325; GFX1250-NEXT: v_cvt_scale_pk16_bf16_bf6 v[6:13], v[0:2], v3 scale_sel:6326; GFX1250-NEXT: s_clause 0x1327; GFX1250-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16328; GFX1250-NEXT: global_store_b128 v[4:5], v[6:9], off329; GFX1250-NEXT: s_endpgm330 %cvt = tail call <16 x bfloat> @llvm.amdgcn.cvt.scale.pk16.bf16.bf6(<3 x i32> %src, i32 %scale, i32 6)331 store <16 x bfloat> %cvt, ptr addrspace(1) %out, align 8332 ret void333}334 335define amdgpu_ps void @test_cvt_scale_pk16_bf16_bf6_sl(<3 x i32> inreg %src, ptr addrspace(1) %out) {336; GFX1250-LABEL: test_cvt_scale_pk16_bf16_bf6_sl:337; GFX1250: ; %bb.0:338; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1339; GFX1250-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v11, s1340; GFX1250-NEXT: v_mov_b32_e32 v12, s2341; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)342; GFX1250-NEXT: v_cvt_scale_pk16_bf16_bf6 v[2:9], v[10:12], 0x64 scale_sel:8343; GFX1250-NEXT: s_clause 0x1344; GFX1250-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16345; GFX1250-NEXT: global_store_b128 v[0:1], v[2:5], off346; GFX1250-NEXT: s_endpgm347 %cvt = tail call <16 x bfloat> @llvm.amdgcn.cvt.scale.pk16.bf16.bf6(<3 x i32> %src, i32 100, i32 8)348 store <16 x bfloat> %cvt, ptr addrspace(1) %out, align 8349 ret void350}351 352define amdgpu_ps void @test_cvt_scale_pk16_f32_fp6_vv(<3 x i32> %src, i32 %scale, ptr addrspace(1) %out) {353; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f32_fp6_vv:354; GFX1250-SDAG: ; %bb.0:355; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1356; GFX1250-SDAG-NEXT: v_cvt_scale_pk16_f32_fp6 v[6:21], v[0:2], v3 scale_sel:5357; GFX1250-SDAG-NEXT: s_clause 0x3358; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[18:21], off offset:48359; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[14:17], off offset:32360; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16361; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[6:9], off362; GFX1250-SDAG-NEXT: s_endpgm363;364; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f32_fp6_vv:365; GFX1250-GISEL: ; %bb.0:366; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1367; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f32_fp6 v[6:21], v[0:2], v3 scale_sel:5368; GFX1250-GISEL-NEXT: s_clause 0x3369; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[6:9], off370; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16371; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[14:17], off offset:32372; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[18:21], off offset:48373; GFX1250-GISEL-NEXT: s_endpgm374 %cvt = tail call <16 x float> @llvm.amdgcn.cvt.scale.pk16.f32.fp6(<3 x i32> %src, i32 %scale, i32 5)375 store <16 x float> %cvt, ptr addrspace(1) %out, align 16376 ret void377}378 379define amdgpu_ps void @test_cvt_scale_pk16_f32_bf6_vv(<3 x i32> %src, i32 %scale, ptr addrspace(1) %out) {380; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f32_bf6_vv:381; GFX1250-SDAG: ; %bb.0:382; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1383; GFX1250-SDAG-NEXT: v_cvt_scale_pk16_f32_bf6 v[6:21], v[0:2], v3 scale_sel:6384; GFX1250-SDAG-NEXT: s_clause 0x3385; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[18:21], off offset:48386; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[14:17], off offset:32387; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16388; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[6:9], off389; GFX1250-SDAG-NEXT: s_endpgm390;391; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f32_bf6_vv:392; GFX1250-GISEL: ; %bb.0:393; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1394; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f32_bf6 v[6:21], v[0:2], v3 scale_sel:6395; GFX1250-GISEL-NEXT: s_clause 0x3396; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[6:9], off397; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16398; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[14:17], off offset:32399; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[18:21], off offset:48400; GFX1250-GISEL-NEXT: s_endpgm401 %cvt = tail call <16 x float> @llvm.amdgcn.cvt.scale.pk16.f32.bf6(<3 x i32> %src, i32 %scale, i32 6)402 store <16 x float> %cvt, ptr addrspace(1) %out, align 16403 ret void404}405