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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950-SDAG %s3; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950-GISEL %s4 5declare <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.bf6.bf16(<32 x bfloat> %src, float %scale)6declare <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.bf6.f16(<32 x half> %src, float %scale)7declare <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.fp6.bf16(<32 x bfloat> %src, float %scale)8declare <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.fp6.f16(<32 x half> %src, float %scale)9 10define amdgpu_ps void @test_scalef32_pk32_bf6_bf16_vv(<32 x bfloat> %src, float %scale, ptr addrspace(1) %out) {11; GFX950-SDAG-LABEL: test_scalef32_pk32_bf6_bf16_vv:12; GFX950-SDAG: ; %bb.0:13; GFX950-SDAG-NEXT: v_mov_b32_e32 v25, v1814; GFX950-SDAG-NEXT: v_mov_b32_e32 v24, v1715; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_bf6_bf16 v[18:23], v[0:15], v1616; GFX950-SDAG-NEXT: global_store_dwordx2 v[24:25], v[22:23], off offset:1617; GFX950-SDAG-NEXT: global_store_dwordx4 v[24:25], v[18:21], off18; GFX950-SDAG-NEXT: s_endpgm19;20; GFX950-GISEL-LABEL: test_scalef32_pk32_bf6_bf16_vv:21; GFX950-GISEL: ; %bb.0:22; GFX950-GISEL-NEXT: v_mov_b32_e32 v25, v1823; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, v1724; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_bf6_bf16 v[18:23], v[0:15], v1625; GFX950-GISEL-NEXT: global_store_dwordx2 v[24:25], v[22:23], off offset:1626; GFX950-GISEL-NEXT: global_store_dwordx4 v[24:25], v[18:21], off27; GFX950-GISEL-NEXT: s_endpgm28 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.bf6.bf16(<32 x bfloat> %src, float %scale)29 store <6 x i32> %cvt, ptr addrspace(1) %out, align 830 ret void31}32 33define amdgpu_ps void @test_scalef32_pk32_bf6_bf16_sl(<32 x bfloat> inreg %src, ptr addrspace(1) %out) {34; GFX950-SDAG-LABEL: test_scalef32_pk32_bf6_bf16_sl:35; GFX950-SDAG: ; %bb.0:36; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s037; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s138; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s239; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s340; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s441; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s542; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s643; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s744; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s845; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s946; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s1047; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s1148; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s1249; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s1350; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s1451; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s1552; GFX950-SDAG-NEXT: s_mov_b32 s0, 0x42c8000053; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_bf6_bf16 v[18:23], v[2:17], s054; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:1655; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[18:21], off56; GFX950-SDAG-NEXT: s_endpgm57;58; GFX950-GISEL-LABEL: test_scalef32_pk32_bf6_bf16_sl:59; GFX950-GISEL: ; %bb.0:60; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, s061; GFX950-GISEL-NEXT: v_mov_b32_e32 v3, s162; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, s263; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, s364; GFX950-GISEL-NEXT: v_mov_b32_e32 v6, s465; GFX950-GISEL-NEXT: v_mov_b32_e32 v7, s566; GFX950-GISEL-NEXT: v_mov_b32_e32 v8, s667; GFX950-GISEL-NEXT: v_mov_b32_e32 v9, s768; GFX950-GISEL-NEXT: v_mov_b32_e32 v10, s869; GFX950-GISEL-NEXT: v_mov_b32_e32 v11, s970; GFX950-GISEL-NEXT: v_mov_b32_e32 v12, s1071; GFX950-GISEL-NEXT: v_mov_b32_e32 v13, s1172; GFX950-GISEL-NEXT: v_mov_b32_e32 v14, s1273; GFX950-GISEL-NEXT: v_mov_b32_e32 v15, s1374; GFX950-GISEL-NEXT: v_mov_b32_e32 v16, s1475; GFX950-GISEL-NEXT: v_mov_b32_e32 v17, s1576; GFX950-GISEL-NEXT: s_mov_b32 s0, 0x42c8000077; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_bf6_bf16 v[18:23], v[2:17], s078; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:1679; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off80; GFX950-GISEL-NEXT: s_endpgm81 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.bf6.bf16(<32 x bfloat> %src, float 100.0)82 store <6 x i32> %cvt, ptr addrspace(1) %out, align 883 ret void84}85 86define amdgpu_ps void @test_scalef32_pk32_bf6_f16_vv(<32 x half> %src, float %scale, ptr addrspace(1) %out) {87; GFX950-SDAG-LABEL: test_scalef32_pk32_bf6_f16_vv:88; GFX950-SDAG: ; %bb.0:89; GFX950-SDAG-NEXT: v_mov_b32_e32 v25, v1890; GFX950-SDAG-NEXT: v_mov_b32_e32 v24, v1791; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_bf6_f16 v[18:23], v[0:15], v1692; GFX950-SDAG-NEXT: global_store_dwordx2 v[24:25], v[22:23], off offset:1693; GFX950-SDAG-NEXT: global_store_dwordx4 v[24:25], v[18:21], off94; GFX950-SDAG-NEXT: s_endpgm95;96; GFX950-GISEL-LABEL: test_scalef32_pk32_bf6_f16_vv:97; GFX950-GISEL: ; %bb.0:98; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, v1799; GFX950-GISEL-NEXT: v_mov_b32_e32 v25, v18100; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_bf6_f16 v[18:23], v[0:15], v16101; GFX950-GISEL-NEXT: global_store_dwordx4 v[24:25], v[18:21], off102; GFX950-GISEL-NEXT: global_store_dwordx2 v[24:25], v[22:23], off offset:16103; GFX950-GISEL-NEXT: s_endpgm104 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.bf6.f16(<32 x half> %src, float %scale)105 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8106 ret void107}108 109define amdgpu_ps void @test_scalef32_pk32_bf6_f16_sl(<32 x half> inreg %src, ptr addrspace(1) %out) {110; GFX950-SDAG-LABEL: test_scalef32_pk32_bf6_f16_sl:111; GFX950-SDAG: ; %bb.0:112; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0113; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1114; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2115; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3116; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4117; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5118; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6119; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7120; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8121; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9122; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10123; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11124; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12125; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13126; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14127; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15128; GFX950-SDAG-NEXT: s_mov_b32 s0, 0x42c80000129; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_bf6_f16 v[18:23], v[2:17], s0130; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16131; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[18:21], off132; GFX950-SDAG-NEXT: s_endpgm133;134; GFX950-GISEL-LABEL: test_scalef32_pk32_bf6_f16_sl:135; GFX950-GISEL: ; %bb.0:136; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]137; GFX950-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]138; GFX950-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]139; GFX950-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]140; GFX950-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]141; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]142; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]143; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]144; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000145; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_bf6_f16 v[18:23], v[2:17], v24146; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off147; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16148; GFX950-GISEL-NEXT: s_endpgm149 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.bf6.f16(<32 x half> %src, float 100.0)150 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8151 ret void152}153 154define amdgpu_ps void @test_scalef32_pk32_fp6_bf16_vv(<32 x bfloat> %src, float %scale, ptr addrspace(1) %out) {155; GFX950-SDAG-LABEL: test_scalef32_pk32_fp6_bf16_vv:156; GFX950-SDAG: ; %bb.0:157; GFX950-SDAG-NEXT: v_mov_b32_e32 v25, v18158; GFX950-SDAG-NEXT: v_mov_b32_e32 v24, v17159; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_fp6_bf16 v[18:23], v[0:15], v16160; GFX950-SDAG-NEXT: global_store_dwordx2 v[24:25], v[22:23], off offset:16161; GFX950-SDAG-NEXT: global_store_dwordx4 v[24:25], v[18:21], off162; GFX950-SDAG-NEXT: s_endpgm163;164; GFX950-GISEL-LABEL: test_scalef32_pk32_fp6_bf16_vv:165; GFX950-GISEL: ; %bb.0:166; GFX950-GISEL-NEXT: v_mov_b32_e32 v25, v18167; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, v17168; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_fp6_bf16 v[18:23], v[0:15], v16169; GFX950-GISEL-NEXT: global_store_dwordx2 v[24:25], v[22:23], off offset:16170; GFX950-GISEL-NEXT: global_store_dwordx4 v[24:25], v[18:21], off171; GFX950-GISEL-NEXT: s_endpgm172 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.fp6.bf16(<32 x bfloat> %src, float %scale)173 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8174 ret void175}176 177define amdgpu_ps void @test_scalef32_pk32_fp6_bf16_sl(<32 x bfloat> inreg %src, ptr addrspace(1) %out) {178; GFX950-SDAG-LABEL: test_scalef32_pk32_fp6_bf16_sl:179; GFX950-SDAG: ; %bb.0:180; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0181; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1182; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2183; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3184; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4185; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5186; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6187; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7188; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8189; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9190; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10191; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11192; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12193; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13194; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14195; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15196; GFX950-SDAG-NEXT: s_mov_b32 s0, 0x42c80000197; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_fp6_bf16 v[18:23], v[2:17], s0198; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16199; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[18:21], off200; GFX950-SDAG-NEXT: s_endpgm201;202; GFX950-GISEL-LABEL: test_scalef32_pk32_fp6_bf16_sl:203; GFX950-GISEL: ; %bb.0:204; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, s0205; GFX950-GISEL-NEXT: v_mov_b32_e32 v3, s1206; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, s2207; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, s3208; GFX950-GISEL-NEXT: v_mov_b32_e32 v6, s4209; GFX950-GISEL-NEXT: v_mov_b32_e32 v7, s5210; GFX950-GISEL-NEXT: v_mov_b32_e32 v8, s6211; GFX950-GISEL-NEXT: v_mov_b32_e32 v9, s7212; GFX950-GISEL-NEXT: v_mov_b32_e32 v10, s8213; GFX950-GISEL-NEXT: v_mov_b32_e32 v11, s9214; GFX950-GISEL-NEXT: v_mov_b32_e32 v12, s10215; GFX950-GISEL-NEXT: v_mov_b32_e32 v13, s11216; GFX950-GISEL-NEXT: v_mov_b32_e32 v14, s12217; GFX950-GISEL-NEXT: v_mov_b32_e32 v15, s13218; GFX950-GISEL-NEXT: v_mov_b32_e32 v16, s14219; GFX950-GISEL-NEXT: v_mov_b32_e32 v17, s15220; GFX950-GISEL-NEXT: s_mov_b32 s0, 0x42c80000221; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_fp6_bf16 v[18:23], v[2:17], s0222; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16223; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off224; GFX950-GISEL-NEXT: s_endpgm225 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.fp6.bf16(<32 x bfloat> %src, float 100.0)226 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8227 ret void228}229 230define amdgpu_ps void @test_scalef32_pk32_fp6_f16_vv(<32 x half> %src, float %scale, ptr addrspace(1) %out) {231; GFX950-SDAG-LABEL: test_scalef32_pk32_fp6_f16_vv:232; GFX950-SDAG: ; %bb.0:233; GFX950-SDAG-NEXT: v_mov_b32_e32 v25, v18234; GFX950-SDAG-NEXT: v_mov_b32_e32 v24, v17235; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_fp6_f16 v[18:23], v[0:15], v16236; GFX950-SDAG-NEXT: global_store_dwordx2 v[24:25], v[22:23], off offset:16237; GFX950-SDAG-NEXT: global_store_dwordx4 v[24:25], v[18:21], off238; GFX950-SDAG-NEXT: s_endpgm239;240; GFX950-GISEL-LABEL: test_scalef32_pk32_fp6_f16_vv:241; GFX950-GISEL: ; %bb.0:242; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, v17243; GFX950-GISEL-NEXT: v_mov_b32_e32 v25, v18244; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_fp6_f16 v[18:23], v[0:15], v16245; GFX950-GISEL-NEXT: global_store_dwordx4 v[24:25], v[18:21], off246; GFX950-GISEL-NEXT: global_store_dwordx2 v[24:25], v[22:23], off offset:16247; GFX950-GISEL-NEXT: s_endpgm248 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.fp6.f16(<32 x half> %src, float %scale)249 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8250 ret void251}252 253define amdgpu_ps void @test_scalef32_pk32_fp6_f16_sl(<32 x half> inreg %src, ptr addrspace(1) %out) {254; GFX950-SDAG-LABEL: test_scalef32_pk32_fp6_f16_sl:255; GFX950-SDAG: ; %bb.0:256; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0257; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1258; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2259; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3260; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4261; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5262; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6263; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7264; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8265; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9266; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10267; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11268; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12269; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13270; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14271; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15272; GFX950-SDAG-NEXT: s_mov_b32 s0, 0x42c80000273; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_fp6_f16 v[18:23], v[2:17], s0274; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16275; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[18:21], off276; GFX950-SDAG-NEXT: s_endpgm277;278; GFX950-GISEL-LABEL: test_scalef32_pk32_fp6_f16_sl:279; GFX950-GISEL: ; %bb.0:280; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]281; GFX950-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]282; GFX950-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]283; GFX950-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]284; GFX950-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]285; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]286; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]287; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]288; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000289; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_fp6_f16 v[18:23], v[2:17], v24290; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off291; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16292; GFX950-GISEL-NEXT: s_endpgm293 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.fp6.f16(<32 x half> %src, float 100.0)294 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8295 ret void296}297 298define amdgpu_ps void @test_scalef32_pk32_bf6_bf16_vv_inreg_src(<32 x bfloat> inreg %src, float %scale, ptr addrspace(1) %out) {299; GFX950-SDAG-LABEL: test_scalef32_pk32_bf6_bf16_vv_inreg_src:300; GFX950-SDAG: ; %bb.0:301; GFX950-SDAG-NEXT: v_mov_b32_e32 v25, v2302; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0303; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1304; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2305; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3306; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4307; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5308; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6309; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7310; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8311; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9312; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10313; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11314; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12315; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13316; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14317; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15318; GFX950-SDAG-NEXT: v_mov_b32_e32 v24, v1319; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_bf6_bf16 v[18:23], v[2:17], v0320; GFX950-SDAG-NEXT: global_store_dwordx2 v[24:25], v[22:23], off offset:16321; GFX950-SDAG-NEXT: global_store_dwordx4 v[24:25], v[18:21], off322; GFX950-SDAG-NEXT: s_endpgm323;324; GFX950-GISEL-LABEL: test_scalef32_pk32_bf6_bf16_vv_inreg_src:325; GFX950-GISEL: ; %bb.0:326; GFX950-GISEL-NEXT: v_mov_b32_e32 v25, v2327; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, s0328; GFX950-GISEL-NEXT: v_mov_b32_e32 v3, s1329; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, s2330; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, s3331; GFX950-GISEL-NEXT: v_mov_b32_e32 v6, s4332; GFX950-GISEL-NEXT: v_mov_b32_e32 v7, s5333; GFX950-GISEL-NEXT: v_mov_b32_e32 v8, s6334; GFX950-GISEL-NEXT: v_mov_b32_e32 v9, s7335; GFX950-GISEL-NEXT: v_mov_b32_e32 v10, s8336; GFX950-GISEL-NEXT: v_mov_b32_e32 v11, s9337; GFX950-GISEL-NEXT: v_mov_b32_e32 v12, s10338; GFX950-GISEL-NEXT: v_mov_b32_e32 v13, s11339; GFX950-GISEL-NEXT: v_mov_b32_e32 v14, s12340; GFX950-GISEL-NEXT: v_mov_b32_e32 v15, s13341; GFX950-GISEL-NEXT: v_mov_b32_e32 v16, s14342; GFX950-GISEL-NEXT: v_mov_b32_e32 v17, s15343; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, v1344; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_bf6_bf16 v[18:23], v[2:17], v0345; GFX950-GISEL-NEXT: global_store_dwordx2 v[24:25], v[22:23], off offset:16346; GFX950-GISEL-NEXT: global_store_dwordx4 v[24:25], v[18:21], off347; GFX950-GISEL-NEXT: s_endpgm348 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.bf6.bf16(<32 x bfloat> %src, float %scale)349 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8350 ret void351}352 353define amdgpu_ps void @test_scalef32_pk32_bf6_bf16_sl_inreg_src(<32 x bfloat> inreg %src, ptr addrspace(1) %out) {354; GFX950-SDAG-LABEL: test_scalef32_pk32_bf6_bf16_sl_inreg_src:355; GFX950-SDAG: ; %bb.0:356; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0357; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1358; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2359; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3360; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4361; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5362; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6363; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7364; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8365; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9366; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10367; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11368; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12369; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13370; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14371; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15372; GFX950-SDAG-NEXT: s_mov_b32 s0, 0x42c80000373; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_bf6_bf16 v[18:23], v[2:17], s0374; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16375; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[18:21], off376; GFX950-SDAG-NEXT: s_endpgm377;378; GFX950-GISEL-LABEL: test_scalef32_pk32_bf6_bf16_sl_inreg_src:379; GFX950-GISEL: ; %bb.0:380; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, s0381; GFX950-GISEL-NEXT: v_mov_b32_e32 v3, s1382; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, s2383; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, s3384; GFX950-GISEL-NEXT: v_mov_b32_e32 v6, s4385; GFX950-GISEL-NEXT: v_mov_b32_e32 v7, s5386; GFX950-GISEL-NEXT: v_mov_b32_e32 v8, s6387; GFX950-GISEL-NEXT: v_mov_b32_e32 v9, s7388; GFX950-GISEL-NEXT: v_mov_b32_e32 v10, s8389; GFX950-GISEL-NEXT: v_mov_b32_e32 v11, s9390; GFX950-GISEL-NEXT: v_mov_b32_e32 v12, s10391; GFX950-GISEL-NEXT: v_mov_b32_e32 v13, s11392; GFX950-GISEL-NEXT: v_mov_b32_e32 v14, s12393; GFX950-GISEL-NEXT: v_mov_b32_e32 v15, s13394; GFX950-GISEL-NEXT: v_mov_b32_e32 v16, s14395; GFX950-GISEL-NEXT: v_mov_b32_e32 v17, s15396; GFX950-GISEL-NEXT: s_mov_b32 s0, 0x42c80000397; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_bf6_bf16 v[18:23], v[2:17], s0398; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16399; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off400; GFX950-GISEL-NEXT: s_endpgm401 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.bf6.bf16(<32 x bfloat> %src, float 100.0)402 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8403 ret void404}405 406define amdgpu_ps void @test_scalef32_pk32_bf6_f16_vv_inreg_src(<32 x half> inreg %src, float %scale, ptr addrspace(1) %out) {407; GFX950-SDAG-LABEL: test_scalef32_pk32_bf6_f16_vv_inreg_src:408; GFX950-SDAG: ; %bb.0:409; GFX950-SDAG-NEXT: v_mov_b32_e32 v25, v2410; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0411; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1412; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2413; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3414; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4415; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5416; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6417; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7418; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8419; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9420; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10421; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11422; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12423; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13424; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14425; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15426; GFX950-SDAG-NEXT: v_mov_b32_e32 v24, v1427; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_bf6_f16 v[18:23], v[2:17], v0428; GFX950-SDAG-NEXT: global_store_dwordx2 v[24:25], v[22:23], off offset:16429; GFX950-SDAG-NEXT: global_store_dwordx4 v[24:25], v[18:21], off430; GFX950-SDAG-NEXT: s_endpgm431;432; GFX950-GISEL-LABEL: test_scalef32_pk32_bf6_f16_vv_inreg_src:433; GFX950-GISEL: ; %bb.0:434; GFX950-GISEL-NEXT: v_mov_b32_e32 v25, v2435; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]436; GFX950-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]437; GFX950-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]438; GFX950-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]439; GFX950-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]440; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]441; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]442; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]443; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, v1444; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_bf6_f16 v[18:23], v[2:17], v0445; GFX950-GISEL-NEXT: global_store_dwordx4 v[24:25], v[18:21], off446; GFX950-GISEL-NEXT: global_store_dwordx2 v[24:25], v[22:23], off offset:16447; GFX950-GISEL-NEXT: s_endpgm448 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.bf6.f16(<32 x half> %src, float %scale)449 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8450 ret void451}452 453define amdgpu_ps void @test_scalef32_pk32_bf6_f16_sl_inreg_src(<32 x half> inreg %src, ptr addrspace(1) %out) {454; GFX950-SDAG-LABEL: test_scalef32_pk32_bf6_f16_sl_inreg_src:455; GFX950-SDAG: ; %bb.0:456; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0457; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1458; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2459; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3460; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4461; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5462; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6463; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7464; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8465; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9466; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10467; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11468; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12469; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13470; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14471; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15472; GFX950-SDAG-NEXT: s_mov_b32 s0, 0x42c80000473; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_bf6_f16 v[18:23], v[2:17], s0474; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16475; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[18:21], off476; GFX950-SDAG-NEXT: s_endpgm477;478; GFX950-GISEL-LABEL: test_scalef32_pk32_bf6_f16_sl_inreg_src:479; GFX950-GISEL: ; %bb.0:480; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]481; GFX950-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]482; GFX950-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]483; GFX950-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]484; GFX950-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]485; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]486; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]487; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]488; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000489; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_bf6_f16 v[18:23], v[2:17], v24490; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off491; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16492; GFX950-GISEL-NEXT: s_endpgm493 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.bf6.f16(<32 x half> %src, float 100.0)494 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8495 ret void496}497 498define amdgpu_ps void @test_scalef32_pk32_fp6_bf16_vv_inreg_src(<32 x bfloat> inreg %src, float %scale, ptr addrspace(1) %out) {499; GFX950-SDAG-LABEL: test_scalef32_pk32_fp6_bf16_vv_inreg_src:500; GFX950-SDAG: ; %bb.0:501; GFX950-SDAG-NEXT: v_mov_b32_e32 v25, v2502; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0503; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1504; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2505; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3506; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4507; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5508; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6509; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7510; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8511; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9512; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10513; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11514; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12515; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13516; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14517; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15518; GFX950-SDAG-NEXT: v_mov_b32_e32 v24, v1519; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_fp6_bf16 v[18:23], v[2:17], v0520; GFX950-SDAG-NEXT: global_store_dwordx2 v[24:25], v[22:23], off offset:16521; GFX950-SDAG-NEXT: global_store_dwordx4 v[24:25], v[18:21], off522; GFX950-SDAG-NEXT: s_endpgm523;524; GFX950-GISEL-LABEL: test_scalef32_pk32_fp6_bf16_vv_inreg_src:525; GFX950-GISEL: ; %bb.0:526; GFX950-GISEL-NEXT: v_mov_b32_e32 v25, v2527; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, s0528; GFX950-GISEL-NEXT: v_mov_b32_e32 v3, s1529; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, s2530; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, s3531; GFX950-GISEL-NEXT: v_mov_b32_e32 v6, s4532; GFX950-GISEL-NEXT: v_mov_b32_e32 v7, s5533; GFX950-GISEL-NEXT: v_mov_b32_e32 v8, s6534; GFX950-GISEL-NEXT: v_mov_b32_e32 v9, s7535; GFX950-GISEL-NEXT: v_mov_b32_e32 v10, s8536; GFX950-GISEL-NEXT: v_mov_b32_e32 v11, s9537; GFX950-GISEL-NEXT: v_mov_b32_e32 v12, s10538; GFX950-GISEL-NEXT: v_mov_b32_e32 v13, s11539; GFX950-GISEL-NEXT: v_mov_b32_e32 v14, s12540; GFX950-GISEL-NEXT: v_mov_b32_e32 v15, s13541; GFX950-GISEL-NEXT: v_mov_b32_e32 v16, s14542; GFX950-GISEL-NEXT: v_mov_b32_e32 v17, s15543; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, v1544; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_fp6_bf16 v[18:23], v[2:17], v0545; GFX950-GISEL-NEXT: global_store_dwordx2 v[24:25], v[22:23], off offset:16546; GFX950-GISEL-NEXT: global_store_dwordx4 v[24:25], v[18:21], off547; GFX950-GISEL-NEXT: s_endpgm548 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.fp6.bf16(<32 x bfloat> %src, float %scale)549 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8550 ret void551}552 553define amdgpu_ps void @test_scalef32_pk32_fp6_bf16_sl_inreg_src(<32 x bfloat> inreg %src, ptr addrspace(1) %out) {554; GFX950-SDAG-LABEL: test_scalef32_pk32_fp6_bf16_sl_inreg_src:555; GFX950-SDAG: ; %bb.0:556; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0557; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1558; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2559; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3560; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4561; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5562; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6563; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7564; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8565; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9566; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10567; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11568; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12569; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13570; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14571; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15572; GFX950-SDAG-NEXT: s_mov_b32 s0, 0x42c80000573; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_fp6_bf16 v[18:23], v[2:17], s0574; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16575; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[18:21], off576; GFX950-SDAG-NEXT: s_endpgm577;578; GFX950-GISEL-LABEL: test_scalef32_pk32_fp6_bf16_sl_inreg_src:579; GFX950-GISEL: ; %bb.0:580; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, s0581; GFX950-GISEL-NEXT: v_mov_b32_e32 v3, s1582; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, s2583; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, s3584; GFX950-GISEL-NEXT: v_mov_b32_e32 v6, s4585; GFX950-GISEL-NEXT: v_mov_b32_e32 v7, s5586; GFX950-GISEL-NEXT: v_mov_b32_e32 v8, s6587; GFX950-GISEL-NEXT: v_mov_b32_e32 v9, s7588; GFX950-GISEL-NEXT: v_mov_b32_e32 v10, s8589; GFX950-GISEL-NEXT: v_mov_b32_e32 v11, s9590; GFX950-GISEL-NEXT: v_mov_b32_e32 v12, s10591; GFX950-GISEL-NEXT: v_mov_b32_e32 v13, s11592; GFX950-GISEL-NEXT: v_mov_b32_e32 v14, s12593; GFX950-GISEL-NEXT: v_mov_b32_e32 v15, s13594; GFX950-GISEL-NEXT: v_mov_b32_e32 v16, s14595; GFX950-GISEL-NEXT: v_mov_b32_e32 v17, s15596; GFX950-GISEL-NEXT: s_mov_b32 s0, 0x42c80000597; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_fp6_bf16 v[18:23], v[2:17], s0598; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16599; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off600; GFX950-GISEL-NEXT: s_endpgm601 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.fp6.bf16(<32 x bfloat> %src, float 100.0)602 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8603 ret void604}605 606define amdgpu_ps void @test_scalef32_pk32_fp6_f16_vv_inreg_src(<32 x half> inreg %src, float %scale, ptr addrspace(1) %out) {607; GFX950-SDAG-LABEL: test_scalef32_pk32_fp6_f16_vv_inreg_src:608; GFX950-SDAG: ; %bb.0:609; GFX950-SDAG-NEXT: v_mov_b32_e32 v25, v2610; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0611; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1612; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2613; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3614; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4615; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5616; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6617; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7618; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8619; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9620; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10621; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11622; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12623; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13624; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14625; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15626; GFX950-SDAG-NEXT: v_mov_b32_e32 v24, v1627; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_fp6_f16 v[18:23], v[2:17], v0628; GFX950-SDAG-NEXT: global_store_dwordx2 v[24:25], v[22:23], off offset:16629; GFX950-SDAG-NEXT: global_store_dwordx4 v[24:25], v[18:21], off630; GFX950-SDAG-NEXT: s_endpgm631;632; GFX950-GISEL-LABEL: test_scalef32_pk32_fp6_f16_vv_inreg_src:633; GFX950-GISEL: ; %bb.0:634; GFX950-GISEL-NEXT: v_mov_b32_e32 v25, v2635; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]636; GFX950-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]637; GFX950-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]638; GFX950-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]639; GFX950-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]640; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]641; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]642; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]643; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, v1644; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_fp6_f16 v[18:23], v[2:17], v0645; GFX950-GISEL-NEXT: global_store_dwordx4 v[24:25], v[18:21], off646; GFX950-GISEL-NEXT: global_store_dwordx2 v[24:25], v[22:23], off offset:16647; GFX950-GISEL-NEXT: s_endpgm648 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.fp6.f16(<32 x half> %src, float %scale)649 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8650 ret void651}652 653define amdgpu_ps void @test_scalef32_pk32_fp6_f16_sl_inreg_src(<32 x half> inreg %src, ptr addrspace(1) %out) {654; GFX950-SDAG-LABEL: test_scalef32_pk32_fp6_f16_sl_inreg_src:655; GFX950-SDAG: ; %bb.0:656; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0657; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1658; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2659; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3660; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4661; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5662; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6663; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7664; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8665; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9666; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10667; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11668; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12669; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13670; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14671; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15672; GFX950-SDAG-NEXT: s_mov_b32 s0, 0x42c80000673; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_fp6_f16 v[18:23], v[2:17], s0674; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16675; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[18:21], off676; GFX950-SDAG-NEXT: s_endpgm677;678; GFX950-GISEL-LABEL: test_scalef32_pk32_fp6_f16_sl_inreg_src:679; GFX950-GISEL: ; %bb.0:680; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]681; GFX950-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]682; GFX950-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]683; GFX950-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]684; GFX950-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]685; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]686; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]687; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]688; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000689; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_fp6_f16 v[18:23], v[2:17], v24690; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off691; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16692; GFX950-GISEL-NEXT: s_endpgm693 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.fp6.f16(<32 x half> %src, float 100.0)694 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8695 ret void696}697 698