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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-SDAG %s3; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-GISEL %s4 5declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f32(<16 x float> %src, float %scale)6declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f32(<16 x float> %src, float %scale)7declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.bf16(<16 x bfloat> %src, float %scale)8declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f16(<16 x half> %src, float %scale)9declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.bf16(<16 x bfloat> %src, float %scale)10declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f16(<16 x half> %src, float %scale)11 12define amdgpu_ps void @test_scalef32_pk16_bf6_f32_vv(<16 x float> %src, float %scale, ptr addrspace(1) %out) {13; GFX1210-SDAG-LABEL: test_scalef32_pk16_bf6_f32_vv:14; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f32_vv:15; GFX1250-SDAG: ; %bb.0:16; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 117; GFX1250-SDAG-NEXT: v_dual_mov_b32 v23, v18 :: v_dual_mov_b32 v22, v1718; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_f32 v[18:20], v[0:15], v1619; GFX1250-SDAG-NEXT: global_store_b96 v[22:23], v[18:20], off20; GFX1250-SDAG-NEXT: s_endpgm21;22; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_f32_vv:23; GFX1250-GISEL: ; %bb.0:24; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 125; GFX1250-GISEL-NEXT: v_dual_mov_b32 v22, v17 :: v_dual_mov_b32 v23, v1826; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_f32 v[18:20], v[0:15], v1627; GFX1250-GISEL-NEXT: global_store_b96 v[22:23], v[18:20], off28; GFX1250-GISEL-NEXT: s_endpgm29 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f32(<16 x float> %src, float %scale)30 store <3 x i32> %cvt, ptr addrspace(1) %out, align 831 ret void32}33 34define amdgpu_ps void @test_scalef32_pk16_bf6_f32_sl(<16 x float> inreg %src, ptr addrspace(1) %out) {35; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f32_sl:36; GFX1250-SDAG: ; %bb.0:37; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 138; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s139; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s340; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s541; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s742; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s943; GFX1250-SDAG-NEXT: v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s1144; GFX1250-SDAG-NEXT: v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, s1345; GFX1250-SDAG-NEXT: v_dual_mov_b32 v16, s14 :: v_dual_mov_b32 v17, s1546; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)47; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_f32 v[18:20], v[2:17], 0x42c8000048; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[18:20], off49; GFX1250-SDAG-NEXT: s_endpgm50;51; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_f32_sl:52; GFX1250-GISEL: ; %bb.0:53; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 154; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]55; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]56; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]57; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]58; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]59; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]60; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]61; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]62; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)63; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_f32 v[18:20], v[2:17], 0x42c8000064; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[18:20], off65; GFX1250-GISEL-NEXT: s_endpgm66 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f32(<16 x float> %src, float 100.0)67 store <3 x i32> %cvt, ptr addrspace(1) %out, align 868 ret void69}70 71define amdgpu_ps void @test_scalef32_pk16_fp6_f32_vv(<16 x float> %src, float %scale, ptr addrspace(1) %out) {72; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_f32_vv:73; GFX1250-SDAG: ; %bb.0:74; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 175; GFX1250-SDAG-NEXT: v_dual_mov_b32 v23, v18 :: v_dual_mov_b32 v22, v1776; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_f32 v[18:20], v[0:15], v1677; GFX1250-SDAG-NEXT: global_store_b96 v[22:23], v[18:20], off78; GFX1250-SDAG-NEXT: s_endpgm79;80; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_f32_vv:81; GFX1250-GISEL: ; %bb.0:82; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 183; GFX1250-GISEL-NEXT: v_dual_mov_b32 v22, v17 :: v_dual_mov_b32 v23, v1884; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_f32 v[18:20], v[0:15], v1685; GFX1250-GISEL-NEXT: global_store_b96 v[22:23], v[18:20], off86; GFX1250-GISEL-NEXT: s_endpgm87 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f32(<16 x float> %src, float %scale)88 store <3 x i32> %cvt, ptr addrspace(1) %out, align 889 ret void90}91 92define amdgpu_ps void @test_scalef32_pk16_fp6_f32_sl(<16 x float> inreg %src, ptr addrspace(1) %out) {93; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_f32_sl:94; GFX1250-SDAG: ; %bb.0:95; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 196; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s197; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s398; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s599; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7100; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9101; GFX1250-SDAG-NEXT: v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s11102; GFX1250-SDAG-NEXT: v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, s13103; GFX1250-SDAG-NEXT: v_dual_mov_b32 v16, s14 :: v_dual_mov_b32 v17, s15104; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)105; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_f32 v[18:20], v[2:17], 0x42c80000106; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[18:20], off107; GFX1250-SDAG-NEXT: s_endpgm108;109; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_f32_sl:110; GFX1250-GISEL: ; %bb.0:111; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1112; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]113; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]114; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]115; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]116; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]117; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]118; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]119; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]120; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)121; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_f32 v[18:20], v[2:17], 0x42c80000122; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[18:20], off123; GFX1250-GISEL-NEXT: s_endpgm124 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f32(<16 x float> %src, float 100.0)125 store <3 x i32> %cvt, ptr addrspace(1) %out, align 8126 ret void127}128 129define amdgpu_ps void @test_scalef32_pk16_bf6_bf16_vv(<16 x bfloat> %src, float %scale, ptr addrspace(1) %out) {130; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_bf16_vv:131; GFX1250-SDAG: ; %bb.0:132; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1133; GFX1250-SDAG-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9134; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[0:7], v8135; GFX1250-SDAG-NEXT: global_store_b96 v[14:15], v[10:12], off136; GFX1250-SDAG-NEXT: s_endpgm137;138; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_bf16_vv:139; GFX1250-GISEL: ; %bb.0:140; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1141; GFX1250-GISEL-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9142; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[0:7], v8143; GFX1250-GISEL-NEXT: global_store_b96 v[14:15], v[10:12], off144; GFX1250-GISEL-NEXT: s_endpgm145 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.bf16(<16 x bfloat> %src, float %scale)146 store <3 x i32> %cvt, ptr addrspace(1) %out, align 8147 ret void148}149 150define amdgpu_ps void @test_scalef32_pk16_bf6_bf16_sl(<16 x bfloat> inreg %src, ptr addrspace(1) %out) {151; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_bf16_sl:152; GFX1250-SDAG: ; %bb.0:153; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1154; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1155; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3156; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5157; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7158; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)159; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[2:9], 0x42c80000160; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[10:12], off161; GFX1250-SDAG-NEXT: s_endpgm162;163; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_bf16_sl:164; GFX1250-GISEL: ; %bb.0:165; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1166; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1167; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3168; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5169; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7170; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)171; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[2:9], 0x42c80000172; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[10:12], off173; GFX1250-GISEL-NEXT: s_endpgm174 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.bf16(<16 x bfloat> %src, float 100.0)175 store <3 x i32> %cvt, ptr addrspace(1) %out, align 8176 ret void177}178 179define amdgpu_ps void @test_scalef32_pk16_bf6_f16_vv(<16 x half> %src, float %scale, ptr addrspace(1) %out) {180; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f16_vv:181; GFX1250-SDAG: ; %bb.0:182; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1183; GFX1250-SDAG-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9184; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[0:7], v8185; GFX1250-SDAG-NEXT: global_store_b96 v[14:15], v[10:12], off186; GFX1250-SDAG-NEXT: s_endpgm187;188; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_f16_vv:189; GFX1250-GISEL: ; %bb.0:190; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1191; GFX1250-GISEL-NEXT: v_dual_mov_b32 v14, v9 :: v_dual_mov_b32 v15, v10192; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[0:7], v8193; GFX1250-GISEL-NEXT: global_store_b96 v[14:15], v[10:12], off194; GFX1250-GISEL-NEXT: s_endpgm195 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f16(<16 x half> %src, float %scale)196 store <3 x i32> %cvt, ptr addrspace(1) %out, align 8197 ret void198}199 200define amdgpu_ps void @test_scalef32_pk16_bf6_f16_sl(<16 x half> inreg %src, ptr addrspace(1) %out) {201; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f16_sl:202; GFX1250-SDAG: ; %bb.0:203; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1204; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1205; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3206; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5207; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7208; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)209; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[2:9], 0x42c80000210; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[10:12], off211; GFX1250-SDAG-NEXT: s_endpgm212;213; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_f16_sl:214; GFX1250-GISEL: ; %bb.0:215; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1216; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]217; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]218; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]219; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]220; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)221; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[2:9], 0x42c80000222; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[10:12], off223; GFX1250-GISEL-NEXT: s_endpgm224 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f16(<16 x half> %src, float 100.0)225 store <3 x i32> %cvt, ptr addrspace(1) %out, align 8226 ret void227}228 229define amdgpu_ps void @test_scalef32_pk16_fp6_bf16_vv(<16 x bfloat> %src, float %scale, ptr addrspace(1) %out) {230; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_bf16_vv:231; GFX1250-SDAG: ; %bb.0:232; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1233; GFX1250-SDAG-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9234; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[0:7], v8235; GFX1250-SDAG-NEXT: global_store_b96 v[14:15], v[10:12], off236; GFX1250-SDAG-NEXT: s_endpgm237;238; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_bf16_vv:239; GFX1250-GISEL: ; %bb.0:240; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1241; GFX1250-GISEL-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9242; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[0:7], v8243; GFX1250-GISEL-NEXT: global_store_b96 v[14:15], v[10:12], off244; GFX1250-GISEL-NEXT: s_endpgm245 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.bf16(<16 x bfloat> %src, float %scale)246 store <3 x i32> %cvt, ptr addrspace(1) %out, align 8247 ret void248}249 250define amdgpu_ps void @test_scalef32_pk16_fp6_bf16_sl(<16 x bfloat> inreg %src, ptr addrspace(1) %out) {251; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_bf16_sl:252; GFX1250-SDAG: ; %bb.0:253; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1254; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1255; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3256; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5257; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7258; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)259; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[2:9], 0x42c80000260; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[10:12], off261; GFX1250-SDAG-NEXT: s_endpgm262;263; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_bf16_sl:264; GFX1250-GISEL: ; %bb.0:265; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1266; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1267; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3268; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5269; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7270; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)271; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[2:9], 0x42c80000272; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[10:12], off273; GFX1250-GISEL-NEXT: s_endpgm274 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.bf16(<16 x bfloat> %src, float 100.0)275 store <3 x i32> %cvt, ptr addrspace(1) %out, align 8276 ret void277}278 279define amdgpu_ps void @test_scalef32_pk16_fp6_f16_vv(<16 x half> %src, float %scale, ptr addrspace(1) %out) {280; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_f16_vv:281; GFX1250-SDAG: ; %bb.0:282; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1283; GFX1250-SDAG-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9284; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[0:7], v8285; GFX1250-SDAG-NEXT: global_store_b96 v[14:15], v[10:12], off286; GFX1250-SDAG-NEXT: s_endpgm287;288; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_f16_vv:289; GFX1250-GISEL: ; %bb.0:290; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1291; GFX1250-GISEL-NEXT: v_dual_mov_b32 v14, v9 :: v_dual_mov_b32 v15, v10292; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[0:7], v8293; GFX1250-GISEL-NEXT: global_store_b96 v[14:15], v[10:12], off294; GFX1250-GISEL-NEXT: s_endpgm295 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f16(<16 x half> %src, float %scale)296 store <3 x i32> %cvt, ptr addrspace(1) %out, align 8297 ret void298}299 300define amdgpu_ps void @test_scalef32_pk16_fp6_f16_sl(<16 x half> inreg %src, ptr addrspace(1) %out) {301; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_f16_sl:302; GFX1250-SDAG: ; %bb.0:303; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1304; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1305; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3306; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5307; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7308; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)309; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[2:9], 0x42c80000310; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[10:12], off311; GFX1250-SDAG-NEXT: s_endpgm312;313; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_f16_sl:314; GFX1250-GISEL: ; %bb.0:315; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1316; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]317; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]318; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]319; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]320; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)321; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[2:9], 0x42c80000322; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[10:12], off323; GFX1250-GISEL-NEXT: s_endpgm324 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f16(<16 x half> %src, float 100.0)325 store <3 x i32> %cvt, ptr addrspace(1) %out, align 8326 ret void327}328