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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-SDAG %s3; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-GISEL %s4 5declare <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.bf16(<8 x bfloat> %src, float %scale)6declare <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.bf16(<8 x bfloat> %src, float %scale)7declare <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f16(<8 x half> %src, float %scale)8declare <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f16(<8 x half> %src, float %scale)9declare <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f32(<8 x float> %src, float %scale)10declare <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f32(<8 x float> %src, float %scale)11declare i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f32(<8 x float> %src, float %scale)12declare i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f16(<8 x half> %src, float %scale)13declare i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.bf16(<8 x bfloat> %src, float %scale)14 15define amdgpu_ps void @test_scalef32_pk8_fp8_bf16_vv(<8 x bfloat> %src, float %scale, ptr addrspace(1) %out) {16; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_bf16_vv:17; GFX1250-SDAG: ; %bb.0:18; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 119; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v520; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp8_bf16 v[8:9], v[0:3], v421; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off22; GFX1250-SDAG-NEXT: s_endpgm23;24; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_bf16_vv:25; GFX1250-GISEL: ; %bb.0:26; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 127; GFX1250-GISEL-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v528; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp8_bf16 v[8:9], v[0:3], v429; GFX1250-GISEL-NEXT: global_store_b64 v[6:7], v[8:9], off30; GFX1250-GISEL-NEXT: s_endpgm31 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.bf16(<8 x bfloat> %src, float %scale)32 store <2 x i32> %cvt, ptr addrspace(1) %out, align 833 ret void34}35 36define amdgpu_ps void @test_scalef32_pk8_fp8_bf16_sl(<8 x bfloat> inreg %src, ptr addrspace(1) %out) {37; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_bf16_sl:38; GFX1250-SDAG: ; %bb.0:39; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 140; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s141; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s342; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)43; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp8_bf16 v[6:7], v[2:5], 0x42c8000044; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[6:7], off45; GFX1250-SDAG-NEXT: s_endpgm46;47; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_bf16_sl:48; GFX1250-GISEL: ; %bb.0:49; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 150; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s151; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s352; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)53; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp8_bf16 v[6:7], v[2:5], 0x42c8000054; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off55; GFX1250-GISEL-NEXT: s_endpgm56 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.bf16(<8 x bfloat> %src, float 100.0)57 store <2 x i32> %cvt, ptr addrspace(1) %out, align 858 ret void59}60 61define amdgpu_ps void @test_scalef32_pk8_bf8_bf16_vv(<8 x bfloat> %src, float %scale, ptr addrspace(1) %out) {62; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_bf16_vv:63; GFX1250-SDAG: ; %bb.0:64; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 165; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v566; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_bf8_bf16 v[8:9], v[0:3], v467; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off68; GFX1250-SDAG-NEXT: s_endpgm69;70; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_bf16_vv:71; GFX1250-GISEL: ; %bb.0:72; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 173; GFX1250-GISEL-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v574; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_bf8_bf16 v[8:9], v[0:3], v475; GFX1250-GISEL-NEXT: global_store_b64 v[6:7], v[8:9], off76; GFX1250-GISEL-NEXT: s_endpgm77 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.bf16(<8 x bfloat> %src, float %scale)78 store <2 x i32> %cvt, ptr addrspace(1) %out, align 879 ret void80}81 82define amdgpu_ps void @test_scalef32_pk8_bf8_bf16_sl(<8 x bfloat> inreg %src, ptr addrspace(1) %out) {83; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_bf16_sl:84; GFX1250-SDAG: ; %bb.0:85; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 186; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s187; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s388; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)89; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_bf8_bf16 v[6:7], v[2:5], 0x42c8000090; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[6:7], off91; GFX1250-SDAG-NEXT: s_endpgm92;93; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_bf16_sl:94; GFX1250-GISEL: ; %bb.0:95; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 196; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s197; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s398; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)99; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_bf8_bf16 v[6:7], v[2:5], 0x42c80000100; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off101; GFX1250-GISEL-NEXT: s_endpgm102 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.bf16(<8 x bfloat> %src, float 100.0)103 store <2 x i32> %cvt, ptr addrspace(1) %out, align 8104 ret void105}106 107define amdgpu_ps void @test_scalef32_pk8_fp8_f16_vv(<8 x half> %src, float %scale, ptr addrspace(1) %out) {108; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_f16_vv:109; GFX1250-SDAG: ; %bb.0:110; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1111; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5112; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp8_f16 v[8:9], v[0:3], v4113; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off114; GFX1250-SDAG-NEXT: s_endpgm115;116; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_f16_vv:117; GFX1250-GISEL: ; %bb.0:118; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1119; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v9, v6120; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp8_f16 v[6:7], v[0:3], v4121; GFX1250-GISEL-NEXT: global_store_b64 v[8:9], v[6:7], off122; GFX1250-GISEL-NEXT: s_endpgm123 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f16(<8 x half> %src, float %scale)124 store <2 x i32> %cvt, ptr addrspace(1) %out, align 8125 ret void126}127 128define amdgpu_ps void @test_scalef32_pk8_fp8_f16_sl(<8 x half> inreg %src, ptr addrspace(1) %out) {129; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_f16_sl:130; GFX1250-SDAG: ; %bb.0:131; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1132; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1133; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3134; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)135; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp8_f16 v[6:7], v[2:5], 0x42c80000136; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[6:7], off137; GFX1250-SDAG-NEXT: s_endpgm138;139; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_f16_sl:140; GFX1250-GISEL: ; %bb.0:141; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1142; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]143; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]144; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)145; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp8_f16 v[6:7], v[2:5], 0x42c80000146; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off147; GFX1250-GISEL-NEXT: s_endpgm148 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f16(<8 x half> %src, float 100.0)149 store <2 x i32> %cvt, ptr addrspace(1) %out, align 8150 ret void151}152 153define amdgpu_ps void @test_scalef32_pk8_bf8_f16_vv(<8 x half> %src, float %scale, ptr addrspace(1) %out) {154; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_f16_vv:155; GFX1250-SDAG: ; %bb.0:156; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1157; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5158; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_bf8_f16 v[8:9], v[0:3], v4159; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off160; GFX1250-SDAG-NEXT: s_endpgm161;162; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_f16_vv:163; GFX1250-GISEL: ; %bb.0:164; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1165; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v9, v6166; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_bf8_f16 v[6:7], v[0:3], v4167; GFX1250-GISEL-NEXT: global_store_b64 v[8:9], v[6:7], off168; GFX1250-GISEL-NEXT: s_endpgm169 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f16(<8 x half> %src, float %scale)170 store <2 x i32> %cvt, ptr addrspace(1) %out, align 8171 ret void172}173 174define amdgpu_ps void @test_scalef32_pk8_bf8_f16_sl(<8 x half> inreg %src, ptr addrspace(1) %out) {175; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_f16_sl:176; GFX1250-SDAG: ; %bb.0:177; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1178; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1179; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3180; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)181; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_bf8_f16 v[6:7], v[2:5], 0x42c80000182; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[6:7], off183; GFX1250-SDAG-NEXT: s_endpgm184;185; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_f16_sl:186; GFX1250-GISEL: ; %bb.0:187; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1188; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]189; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]190; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)191; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_bf8_f16 v[6:7], v[2:5], 0x42c80000192; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off193; GFX1250-GISEL-NEXT: s_endpgm194 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f16(<8 x half> %src, float 100.0)195 store <2 x i32> %cvt, ptr addrspace(1) %out, align 8196 ret void197}198 199define amdgpu_ps void @test_scalef32_pk8_bf8_f32_vv(<8 x float> %src, float %scale, ptr addrspace(1) %out) {200; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_f32_vv:201; GFX1250-SDAG: ; %bb.0:202; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1203; GFX1250-SDAG-NEXT: v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v10, v9204; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_bf8_f32 v[12:13], v[0:7], v8205; GFX1250-SDAG-NEXT: global_store_b64 v[10:11], v[12:13], off206; GFX1250-SDAG-NEXT: s_endpgm207;208; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_f32_vv:209; GFX1250-GISEL: ; %bb.0:210; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1211; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, v9 :: v_dual_mov_b32 v13, v10212; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[0:7], v8213; GFX1250-GISEL-NEXT: global_store_b64 v[12:13], v[10:11], off214; GFX1250-GISEL-NEXT: s_endpgm215 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f32(<8 x float> %src, float %scale)216 store <2 x i32> %cvt, ptr addrspace(1) %out, align 8217 ret void218}219 220define amdgpu_ps void @test_scalef32_pk8_bf8_f32_sl(<8 x float> inreg %src, ptr addrspace(1) %out) {221; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_f32_sl:222; GFX1250-SDAG: ; %bb.0:223; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1224; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1225; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3226; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5227; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7228; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)229; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[2:9], 0x42c80000230; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[10:11], off231; GFX1250-SDAG-NEXT: s_endpgm232;233; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_f32_sl:234; GFX1250-GISEL: ; %bb.0:235; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1236; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]237; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]238; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]239; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]240; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)241; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[2:9], 0x42c80000242; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[10:11], off243; GFX1250-GISEL-NEXT: s_endpgm244 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f32(<8 x float> %src, float 100.0)245 store <2 x i32> %cvt, ptr addrspace(1) %out, align 8246 ret void247}248 249define amdgpu_ps void @test_scalef32_pk8_fp8_f32_vv(<8 x float> %src, float %scale, ptr addrspace(1) %out) {250; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_f32_vv:251; GFX1250-SDAG: ; %bb.0:252; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1253; GFX1250-SDAG-NEXT: v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v10, v9254; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp8_f32 v[12:13], v[0:7], v8255; GFX1250-SDAG-NEXT: global_store_b64 v[10:11], v[12:13], off256; GFX1250-SDAG-NEXT: s_endpgm257;258; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_f32_vv:259; GFX1250-GISEL: ; %bb.0:260; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1261; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, v9 :: v_dual_mov_b32 v13, v10262; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[0:7], v8263; GFX1250-GISEL-NEXT: global_store_b64 v[12:13], v[10:11], off264; GFX1250-GISEL-NEXT: s_endpgm265 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f32(<8 x float> %src, float %scale)266 store <2 x i32> %cvt, ptr addrspace(1) %out, align 8267 ret void268}269 270define amdgpu_ps void @test_scalef32_pk8_fp8_f32_sl(<8 x float> inreg %src, ptr addrspace(1) %out) {271; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_f32_sl:272; GFX1250-SDAG: ; %bb.0:273; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1274; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1275; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3276; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5277; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7278; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)279; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[2:9], 0x42c80000280; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[10:11], off281; GFX1250-SDAG-NEXT: s_endpgm282;283; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_f32_sl:284; GFX1250-GISEL: ; %bb.0:285; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1286; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]287; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]288; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]289; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]290; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)291; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[2:9], 0x42c80000292; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[10:11], off293; GFX1250-GISEL-NEXT: s_endpgm294 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f32(<8 x float> %src, float 100.0)295 store <2 x i32> %cvt, ptr addrspace(1) %out, align 8296 ret void297}298 299define amdgpu_ps void @test_scalef32_pk8_fp4_f32_vv(<8 x float> %src, float %scale, ptr addrspace(1) %out) {300; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_f32_vv:301; GFX1250-SDAG: ; %bb.0:302; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1303; GFX1250-SDAG-NEXT: v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v10, v9304; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp4_f32 v9, v[0:7], v8305; GFX1250-SDAG-NEXT: global_store_b32 v[10:11], v9, off306; GFX1250-SDAG-NEXT: s_endpgm307;308; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_f32_vv:309; GFX1250-GISEL: ; %bb.0:310; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1311; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, v9 :: v_dual_mov_b32 v13, v10312; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp4_f32 v9, v[0:7], v8313; GFX1250-GISEL-NEXT: global_store_b32 v[12:13], v9, off314; GFX1250-GISEL-NEXT: s_endpgm315 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f32(<8 x float> %src, float %scale)316 store i32 %cvt, ptr addrspace(1) %out, align 4317 ret void318}319 320define amdgpu_ps void @test_scalef32_pk8_fp4_f32_sl(<8 x float> inreg %src, ptr addrspace(1) %out) {321; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_f32_sl:322; GFX1250-SDAG: ; %bb.0:323; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1324; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1325; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3326; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5327; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7328; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)329; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp4_f32 v10, v[2:9], 0x42c80000330; GFX1250-SDAG-NEXT: global_store_b32 v[0:1], v10, off331; GFX1250-SDAG-NEXT: s_endpgm332;333; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_f32_sl:334; GFX1250-GISEL: ; %bb.0:335; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1336; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]337; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]338; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]339; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]340; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)341; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp4_f32 v10, v[2:9], 0x42c80000342; GFX1250-GISEL-NEXT: global_store_b32 v[0:1], v10, off343; GFX1250-GISEL-NEXT: s_endpgm344 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f32(<8 x float> %src, float 100.0)345 store i32 %cvt, ptr addrspace(1) %out, align 4346 ret void347}348 349define amdgpu_ps void @test_scalef32_pk8_fp4_f16_vv(<8 x half> %src, float %scale, ptr addrspace(1) %out) {350; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_f16_vv:351; GFX1250-SDAG: ; %bb.0:352; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1353; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5354; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp4_f16 v5, v[0:3], v4355; GFX1250-SDAG-NEXT: global_store_b32 v[6:7], v5, off356; GFX1250-SDAG-NEXT: s_endpgm357;358; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_f16_vv:359; GFX1250-GISEL: ; %bb.0:360; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1361; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v9, v6362; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp4_f16 v5, v[0:3], v4363; GFX1250-GISEL-NEXT: global_store_b32 v[8:9], v5, off364; GFX1250-GISEL-NEXT: s_endpgm365 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f16(<8 x half> %src, float %scale)366 store i32 %cvt, ptr addrspace(1) %out, align 4367 ret void368}369 370define amdgpu_ps void @test_scalef32_pk8_fp4_f16_sl(<8 x half> inreg %src, ptr addrspace(1) %out) {371; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_f16_sl:372; GFX1250-SDAG: ; %bb.0:373; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1374; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1375; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3376; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)377; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp4_f16 v6, v[2:5], 0x42c80000378; GFX1250-SDAG-NEXT: global_store_b32 v[0:1], v6, off379; GFX1250-SDAG-NEXT: s_endpgm380;381; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_f16_sl:382; GFX1250-GISEL: ; %bb.0:383; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1384; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]385; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]386; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)387; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp4_f16 v6, v[2:5], 0x42c80000388; GFX1250-GISEL-NEXT: global_store_b32 v[0:1], v6, off389; GFX1250-GISEL-NEXT: s_endpgm390 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f16(<8 x half> %src, float 100.0)391 store i32 %cvt, ptr addrspace(1) %out, align 4392 ret void393}394 395define amdgpu_ps void @test_scalef32_pk8_fp4_bf16_vv(<8 x bfloat> %src, float %scale, ptr addrspace(1) %out) {396; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_bf16_vv:397; GFX1250-SDAG: ; %bb.0:398; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1399; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5400; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp4_bf16 v5, v[0:3], v4401; GFX1250-SDAG-NEXT: global_store_b32 v[6:7], v5, off402; GFX1250-SDAG-NEXT: s_endpgm403;404; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_bf16_vv:405; GFX1250-GISEL: ; %bb.0:406; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1407; GFX1250-GISEL-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5408; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp4_bf16 v5, v[0:3], v4409; GFX1250-GISEL-NEXT: global_store_b32 v[6:7], v5, off410; GFX1250-GISEL-NEXT: s_endpgm411 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.bf16(<8 x bfloat> %src, float %scale)412 store i32 %cvt, ptr addrspace(1) %out, align 4413 ret void414}415 416define amdgpu_ps void @test_scalef32_pk8_fp4_bf16_sl(<8 x bfloat> inreg %src, ptr addrspace(1) %out) {417; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_bf16_sl:418; GFX1250-SDAG: ; %bb.0:419; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1420; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1421; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3422; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)423; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp4_bf16 v6, v[2:5], 0x42c80000424; GFX1250-SDAG-NEXT: global_store_b32 v[0:1], v6, off425; GFX1250-SDAG-NEXT: s_endpgm426;427; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_bf16_sl:428; GFX1250-GISEL: ; %bb.0:429; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1430; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1431; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3432; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)433; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp4_bf16 v6, v[2:5], 0x42c80000434; GFX1250-GISEL-NEXT: global_store_b32 v[0:1], v6, off435; GFX1250-GISEL-NEXT: s_endpgm436 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.bf16(<8 x bfloat> %src, float 100.0)437 store i32 %cvt, ptr addrspace(1) %out, align 4438 ret void439}440