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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 -o - %s | FileCheck -check-prefix=GFX950 %s3; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx950 -o - %s | FileCheck -check-prefix=GFX950 %s4 5declare i32 @llvm.amdgcn.cvt.scalef32.sr.bf8.bf16(i32 %old, bfloat %src, i32 %seed, float %scale, i32 %dst_sel)6declare i32 @llvm.amdgcn.cvt.scalef32.sr.bf8.f16(i32 %old, half %src, i32 %seed, float %scale, i32 %dst_sel)7declare i32 @llvm.amdgcn.cvt.scalef32.sr.bf8.f32(i32 %old, float %src, i32 %seed, float %scale, i32 %dst_sel)8declare i32 @llvm.amdgcn.cvt.scalef32.sr.fp8.bf16(i32 %old, bfloat %src, i32 %seed, float %scale, i32 %dst_sel)9declare i32 @llvm.amdgcn.cvt.scalef32.sr.fp8.f16(i32 %old, half %src, i32 %seed, float %scale, i32 %dst_sel)10declare i32 @llvm.amdgcn.cvt.scalef32.sr.fp8.f32(i32 %old, float %src, i32 %seed, float %scale, i32 %dst_sel)11 12define amdgpu_ps void @test_cvt_scalef32_sr_bf8_bf16_dst_sel_0(ptr addrspace(1) %out, bfloat %src, i32 %seed, float %scale) {13; GFX950-LABEL: test_cvt_scalef32_sr_bf8_bf16_dst_sel_0:14; GFX950: ; %bb.0:15; GFX950-NEXT: global_load_dword v5, v[0:1], off16; GFX950-NEXT: s_waitcnt vmcnt(0)17; GFX950-NEXT: v_cvt_scalef32_sr_bf8_bf16 v5, v2, v3, v418; GFX950-NEXT: global_store_dword v[0:1], v5, off19; GFX950-NEXT: s_endpgm20 %old = load i32, ptr addrspace(1) %out, align 421 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.bf8.bf16(i32 %old, bfloat %src, i32 %seed, float %scale, i32 0)22 store i32 %cvt, ptr addrspace(1) %out, align 423 ret void24}25 26define amdgpu_ps void @test_cvt_scalef32_sr_bf8_bf16_dst_sel_1(ptr addrspace(1) %out, bfloat %src, i32 %seed, float %scale) {27; GFX950-LABEL: test_cvt_scalef32_sr_bf8_bf16_dst_sel_1:28; GFX950: ; %bb.0:29; GFX950-NEXT: global_load_dword v5, v[0:1], off30; GFX950-NEXT: s_waitcnt vmcnt(0)31; GFX950-NEXT: v_cvt_scalef32_sr_bf8_bf16 v5, v2, v3, v4 op_sel:[0,0,1,0]32; GFX950-NEXT: global_store_dword v[0:1], v5, off33; GFX950-NEXT: s_endpgm34 %old = load i32, ptr addrspace(1) %out, align 435 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.bf8.bf16(i32 %old, bfloat %src, i32 %seed, float %scale, i32 1)36 store i32 %cvt, ptr addrspace(1) %out, align 437 ret void38}39 40define amdgpu_ps void @test_cvt_scalef32_sr_bf8_bf16_dst_sel_2(ptr addrspace(1) %out, bfloat %src, i32 %seed, float %scale) {41; GFX950-LABEL: test_cvt_scalef32_sr_bf8_bf16_dst_sel_2:42; GFX950: ; %bb.0:43; GFX950-NEXT: global_load_dword v5, v[0:1], off44; GFX950-NEXT: s_waitcnt vmcnt(0)45; GFX950-NEXT: v_cvt_scalef32_sr_bf8_bf16 v5, v2, v3, v4 op_sel:[0,0,0,1]46; GFX950-NEXT: global_store_dword v[0:1], v5, off47; GFX950-NEXT: s_endpgm48 %old = load i32, ptr addrspace(1) %out, align 449 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.bf8.bf16(i32 %old, bfloat %src, i32 %seed, float %scale, i32 2)50 store i32 %cvt, ptr addrspace(1) %out, align 451 ret void52}53 54define amdgpu_ps void @test_cvt_scalef32_sr_bf8_bf16_dst_sel_3(ptr addrspace(1) %out, bfloat %src, i32 %seed, float %scale) {55; GFX950-LABEL: test_cvt_scalef32_sr_bf8_bf16_dst_sel_3:56; GFX950: ; %bb.0:57; GFX950-NEXT: global_load_dword v5, v[0:1], off58; GFX950-NEXT: s_waitcnt vmcnt(0)59; GFX950-NEXT: v_cvt_scalef32_sr_bf8_bf16 v5, v2, v3, v4 op_sel:[0,0,1,1]60; GFX950-NEXT: global_store_dword v[0:1], v5, off61; GFX950-NEXT: s_endpgm62 %old = load i32, ptr addrspace(1) %out, align 463 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.bf8.bf16(i32 %old, bfloat %src, i32 %seed, float %scale, i32 3)64 store i32 %cvt, ptr addrspace(1) %out, align 465 ret void66}67 68define amdgpu_ps void @test_cvt_scalef32_sr_bf8_f16_dst_sel_0(ptr addrspace(1) %out, half %src, i32 %seed, float %scale) {69; GFX950-LABEL: test_cvt_scalef32_sr_bf8_f16_dst_sel_0:70; GFX950: ; %bb.0:71; GFX950-NEXT: global_load_dword v5, v[0:1], off72; GFX950-NEXT: s_waitcnt vmcnt(0)73; GFX950-NEXT: v_cvt_scalef32_sr_bf8_f16 v5, v2, v3, v474; GFX950-NEXT: global_store_dword v[0:1], v5, off75; GFX950-NEXT: s_endpgm76 %old = load i32, ptr addrspace(1) %out, align 477 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.bf8.f16(i32 %old, half %src, i32 %seed, float %scale, i32 0)78 store i32 %cvt, ptr addrspace(1) %out, align 479 ret void80}81 82define amdgpu_ps void @test_cvt_scalef32_sr_bf8_f16_dst_sel_1(ptr addrspace(1) %out, half %src, i32 %seed, float %scale) {83; GFX950-LABEL: test_cvt_scalef32_sr_bf8_f16_dst_sel_1:84; GFX950: ; %bb.0:85; GFX950-NEXT: global_load_dword v5, v[0:1], off86; GFX950-NEXT: s_waitcnt vmcnt(0)87; GFX950-NEXT: v_cvt_scalef32_sr_bf8_f16 v5, v2, v3, v4 op_sel:[0,0,1,0]88; GFX950-NEXT: global_store_dword v[0:1], v5, off89; GFX950-NEXT: s_endpgm90 %old = load i32, ptr addrspace(1) %out, align 491 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.bf8.f16(i32 %old, half %src, i32 %seed, float %scale, i32 1)92 store i32 %cvt, ptr addrspace(1) %out, align 493 ret void94}95 96define amdgpu_ps void @test_cvt_scalef32_sr_bf8_f16_dst_sel_2(ptr addrspace(1) %out, half %src, i32 %seed, float %scale) {97; GFX950-LABEL: test_cvt_scalef32_sr_bf8_f16_dst_sel_2:98; GFX950: ; %bb.0:99; GFX950-NEXT: global_load_dword v5, v[0:1], off100; GFX950-NEXT: s_waitcnt vmcnt(0)101; GFX950-NEXT: v_cvt_scalef32_sr_bf8_f16 v5, v2, v3, v4 op_sel:[0,0,0,1]102; GFX950-NEXT: global_store_dword v[0:1], v5, off103; GFX950-NEXT: s_endpgm104 %old = load i32, ptr addrspace(1) %out, align 4105 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.bf8.f16(i32 %old, half %src, i32 %seed, float %scale, i32 2)106 store i32 %cvt, ptr addrspace(1) %out, align 4107 ret void108}109 110define amdgpu_ps void @test_cvt_scalef32_sr_bf8_f16_dst_sel_3(ptr addrspace(1) %out, half %src, i32 %seed, float %scale) {111; GFX950-LABEL: test_cvt_scalef32_sr_bf8_f16_dst_sel_3:112; GFX950: ; %bb.0:113; GFX950-NEXT: global_load_dword v5, v[0:1], off114; GFX950-NEXT: s_waitcnt vmcnt(0)115; GFX950-NEXT: v_cvt_scalef32_sr_bf8_f16 v5, v2, v3, v4 op_sel:[0,0,1,1]116; GFX950-NEXT: global_store_dword v[0:1], v5, off117; GFX950-NEXT: s_endpgm118 %old = load i32, ptr addrspace(1) %out, align 4119 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.bf8.f16(i32 %old, half %src, i32 %seed, float %scale, i32 3)120 store i32 %cvt, ptr addrspace(1) %out, align 4121 ret void122}123 124define amdgpu_ps void @test_cvt_scalef32_sr_bf8_f32_dst_sel_0(ptr addrspace(1) %out, float %src, i32 %seed, float %scale) {125; GFX950-LABEL: test_cvt_scalef32_sr_bf8_f32_dst_sel_0:126; GFX950: ; %bb.0:127; GFX950-NEXT: global_load_dword v5, v[0:1], off128; GFX950-NEXT: s_waitcnt vmcnt(0)129; GFX950-NEXT: v_cvt_scalef32_sr_bf8_f32 v5, v2, v3, v4130; GFX950-NEXT: global_store_dword v[0:1], v5, off131; GFX950-NEXT: s_endpgm132 %old = load i32, ptr addrspace(1) %out, align 4133 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.bf8.f32(i32 %old, float %src, i32 %seed, float %scale, i32 0)134 store i32 %cvt, ptr addrspace(1) %out, align 4135 ret void136}137 138define amdgpu_ps void @test_cvt_scalef32_sr_bf8_f32_dst_sel_1(ptr addrspace(1) %out, float %src, i32 %seed, float %scale) {139; GFX950-LABEL: test_cvt_scalef32_sr_bf8_f32_dst_sel_1:140; GFX950: ; %bb.0:141; GFX950-NEXT: global_load_dword v5, v[0:1], off142; GFX950-NEXT: s_waitcnt vmcnt(0)143; GFX950-NEXT: v_cvt_scalef32_sr_bf8_f32 v5, v2, v3, v4 op_sel:[0,0,1,0]144; GFX950-NEXT: global_store_dword v[0:1], v5, off145; GFX950-NEXT: s_endpgm146 %old = load i32, ptr addrspace(1) %out, align 4147 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.bf8.f32(i32 %old, float %src, i32 %seed, float %scale, i32 1)148 store i32 %cvt, ptr addrspace(1) %out, align 4149 ret void150}151 152define amdgpu_ps void @test_cvt_scalef32_sr_bf8_f32_dst_sel_2(ptr addrspace(1) %out, float %src, i32 %seed, float %scale) {153; GFX950-LABEL: test_cvt_scalef32_sr_bf8_f32_dst_sel_2:154; GFX950: ; %bb.0:155; GFX950-NEXT: global_load_dword v5, v[0:1], off156; GFX950-NEXT: s_waitcnt vmcnt(0)157; GFX950-NEXT: v_cvt_scalef32_sr_bf8_f32 v5, v2, v3, v4 op_sel:[0,0,0,1]158; GFX950-NEXT: global_store_dword v[0:1], v5, off159; GFX950-NEXT: s_endpgm160 %old = load i32, ptr addrspace(1) %out, align 4161 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.bf8.f32(i32 %old, float %src, i32 %seed, float %scale, i32 2)162 store i32 %cvt, ptr addrspace(1) %out, align 4163 ret void164}165 166define amdgpu_ps void @test_cvt_scalef32_sr_bf8_f32_dst_sel_3(ptr addrspace(1) %out, float %src, i32 %seed, float %scale) {167; GFX950-LABEL: test_cvt_scalef32_sr_bf8_f32_dst_sel_3:168; GFX950: ; %bb.0:169; GFX950-NEXT: global_load_dword v5, v[0:1], off170; GFX950-NEXT: s_waitcnt vmcnt(0)171; GFX950-NEXT: v_cvt_scalef32_sr_bf8_f32 v5, v2, v3, v4 op_sel:[0,0,1,1]172; GFX950-NEXT: global_store_dword v[0:1], v5, off173; GFX950-NEXT: s_endpgm174 %old = load i32, ptr addrspace(1) %out, align 4175 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.bf8.f32(i32 %old, float %src, i32 %seed, float %scale, i32 3)176 store i32 %cvt, ptr addrspace(1) %out, align 4177 ret void178}179 180define amdgpu_ps void @test_cvt_scalef32_sr_fp8_bf16_dst_sel_0(ptr addrspace(1) %out, bfloat %src, i32 %seed, float %scale) {181; GFX950-LABEL: test_cvt_scalef32_sr_fp8_bf16_dst_sel_0:182; GFX950: ; %bb.0:183; GFX950-NEXT: global_load_dword v5, v[0:1], off184; GFX950-NEXT: s_waitcnt vmcnt(0)185; GFX950-NEXT: v_cvt_scalef32_sr_fp8_bf16 v5, v2, v3, v4186; GFX950-NEXT: global_store_dword v[0:1], v5, off187; GFX950-NEXT: s_endpgm188 %old = load i32, ptr addrspace(1) %out, align 4189 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.fp8.bf16(i32 %old, bfloat %src, i32 %seed, float %scale, i32 0)190 store i32 %cvt, ptr addrspace(1) %out, align 4191 ret void192}193 194define amdgpu_ps void @test_cvt_scalef32_sr_fp8_bf16_dst_sel_1(ptr addrspace(1) %out, bfloat %src, i32 %seed, float %scale) {195; GFX950-LABEL: test_cvt_scalef32_sr_fp8_bf16_dst_sel_1:196; GFX950: ; %bb.0:197; GFX950-NEXT: global_load_dword v5, v[0:1], off198; GFX950-NEXT: s_waitcnt vmcnt(0)199; GFX950-NEXT: v_cvt_scalef32_sr_fp8_bf16 v5, v2, v3, v4 op_sel:[0,0,1,0]200; GFX950-NEXT: global_store_dword v[0:1], v5, off201; GFX950-NEXT: s_endpgm202 %old = load i32, ptr addrspace(1) %out, align 4203 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.fp8.bf16(i32 %old, bfloat %src, i32 %seed, float %scale, i32 1)204 store i32 %cvt, ptr addrspace(1) %out, align 4205 ret void206}207 208define amdgpu_ps void @test_cvt_scalef32_sr_fp8_bf16_dst_sel_2(ptr addrspace(1) %out, bfloat %src, i32 %seed, float %scale) {209; GFX950-LABEL: test_cvt_scalef32_sr_fp8_bf16_dst_sel_2:210; GFX950: ; %bb.0:211; GFX950-NEXT: global_load_dword v5, v[0:1], off212; GFX950-NEXT: s_waitcnt vmcnt(0)213; GFX950-NEXT: v_cvt_scalef32_sr_fp8_bf16 v5, v2, v3, v4 op_sel:[0,0,0,1]214; GFX950-NEXT: global_store_dword v[0:1], v5, off215; GFX950-NEXT: s_endpgm216 %old = load i32, ptr addrspace(1) %out, align 4217 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.fp8.bf16(i32 %old, bfloat %src, i32 %seed, float %scale, i32 2)218 store i32 %cvt, ptr addrspace(1) %out, align 4219 ret void220}221 222define amdgpu_ps void @test_cvt_scalef32_sr_fp8_bf16_dst_sel_3(ptr addrspace(1) %out, bfloat %src, i32 %seed, float %scale) {223; GFX950-LABEL: test_cvt_scalef32_sr_fp8_bf16_dst_sel_3:224; GFX950: ; %bb.0:225; GFX950-NEXT: global_load_dword v5, v[0:1], off226; GFX950-NEXT: s_waitcnt vmcnt(0)227; GFX950-NEXT: v_cvt_scalef32_sr_fp8_bf16 v5, v2, v3, v4 op_sel:[0,0,1,1]228; GFX950-NEXT: global_store_dword v[0:1], v5, off229; GFX950-NEXT: s_endpgm230 %old = load i32, ptr addrspace(1) %out, align 4231 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.fp8.bf16(i32 %old, bfloat %src, i32 %seed, float %scale, i32 3)232 store i32 %cvt, ptr addrspace(1) %out, align 4233 ret void234}235 236define amdgpu_ps void @test_cvt_scalef32_sr_fp8_f16_dst_sel_0(ptr addrspace(1) %out, half %src, i32 %seed, float %scale) {237; GFX950-LABEL: test_cvt_scalef32_sr_fp8_f16_dst_sel_0:238; GFX950: ; %bb.0:239; GFX950-NEXT: global_load_dword v5, v[0:1], off240; GFX950-NEXT: s_waitcnt vmcnt(0)241; GFX950-NEXT: v_cvt_scalef32_sr_fp8_f16 v5, v2, v3, v4242; GFX950-NEXT: global_store_dword v[0:1], v5, off243; GFX950-NEXT: s_endpgm244 %old = load i32, ptr addrspace(1) %out, align 4245 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.fp8.f16(i32 %old, half %src, i32 %seed, float %scale, i32 0)246 store i32 %cvt, ptr addrspace(1) %out, align 4247 ret void248}249 250define amdgpu_ps void @test_cvt_scalef32_sr_fp8_f16_dst_sel_1(ptr addrspace(1) %out, half %src, i32 %seed, float %scale) {251; GFX950-LABEL: test_cvt_scalef32_sr_fp8_f16_dst_sel_1:252; GFX950: ; %bb.0:253; GFX950-NEXT: global_load_dword v5, v[0:1], off254; GFX950-NEXT: s_waitcnt vmcnt(0)255; GFX950-NEXT: v_cvt_scalef32_sr_fp8_f16 v5, v2, v3, v4 op_sel:[0,0,1,0]256; GFX950-NEXT: global_store_dword v[0:1], v5, off257; GFX950-NEXT: s_endpgm258 %old = load i32, ptr addrspace(1) %out, align 4259 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.fp8.f16(i32 %old, half %src, i32 %seed, float %scale, i32 1)260 store i32 %cvt, ptr addrspace(1) %out, align 4261 ret void262}263 264define amdgpu_ps void @test_cvt_scalef32_sr_fp8_f16_dst_sel_2(ptr addrspace(1) %out, half %src, i32 %seed, float %scale) {265; GFX950-LABEL: test_cvt_scalef32_sr_fp8_f16_dst_sel_2:266; GFX950: ; %bb.0:267; GFX950-NEXT: global_load_dword v5, v[0:1], off268; GFX950-NEXT: s_waitcnt vmcnt(0)269; GFX950-NEXT: v_cvt_scalef32_sr_fp8_f16 v5, v2, v3, v4 op_sel:[0,0,0,1]270; GFX950-NEXT: global_store_dword v[0:1], v5, off271; GFX950-NEXT: s_endpgm272 %old = load i32, ptr addrspace(1) %out, align 4273 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.fp8.f16(i32 %old, half %src, i32 %seed, float %scale, i32 2)274 store i32 %cvt, ptr addrspace(1) %out, align 4275 ret void276}277 278define amdgpu_ps void @test_cvt_scalef32_sr_fp8_f16_dst_sel_3(ptr addrspace(1) %out, half %src, i32 %seed, float %scale) {279; GFX950-LABEL: test_cvt_scalef32_sr_fp8_f16_dst_sel_3:280; GFX950: ; %bb.0:281; GFX950-NEXT: global_load_dword v5, v[0:1], off282; GFX950-NEXT: s_waitcnt vmcnt(0)283; GFX950-NEXT: v_cvt_scalef32_sr_fp8_f16 v5, v2, v3, v4 op_sel:[0,0,1,1]284; GFX950-NEXT: global_store_dword v[0:1], v5, off285; GFX950-NEXT: s_endpgm286 %old = load i32, ptr addrspace(1) %out, align 4287 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.fp8.f16(i32 %old, half %src, i32 %seed, float %scale, i32 3)288 store i32 %cvt, ptr addrspace(1) %out, align 4289 ret void290}291 292define amdgpu_ps void @test_cvt_scalef32_sr_fp8_f32_dst_sel_0(ptr addrspace(1) %out, float %src, i32 %seed, float %scale) {293; GFX950-LABEL: test_cvt_scalef32_sr_fp8_f32_dst_sel_0:294; GFX950: ; %bb.0:295; GFX950-NEXT: global_load_dword v5, v[0:1], off296; GFX950-NEXT: s_waitcnt vmcnt(0)297; GFX950-NEXT: v_cvt_scalef32_sr_fp8_f32 v5, v2, v3, v4298; GFX950-NEXT: global_store_dword v[0:1], v5, off299; GFX950-NEXT: s_endpgm300 %old = load i32, ptr addrspace(1) %out, align 4301 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.fp8.f32(i32 %old, float %src, i32 %seed, float %scale, i32 0)302 store i32 %cvt, ptr addrspace(1) %out, align 4303 ret void304}305 306define amdgpu_ps void @test_cvt_scalef32_sr_fp8_f32_dst_sel_1(ptr addrspace(1) %out, float %src, i32 %seed, float %scale) {307; GFX950-LABEL: test_cvt_scalef32_sr_fp8_f32_dst_sel_1:308; GFX950: ; %bb.0:309; GFX950-NEXT: global_load_dword v5, v[0:1], off310; GFX950-NEXT: s_waitcnt vmcnt(0)311; GFX950-NEXT: v_cvt_scalef32_sr_fp8_f32 v5, v2, v3, v4 op_sel:[0,0,1,0]312; GFX950-NEXT: global_store_dword v[0:1], v5, off313; GFX950-NEXT: s_endpgm314 %old = load i32, ptr addrspace(1) %out, align 4315 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.fp8.f32(i32 %old, float %src, i32 %seed, float %scale, i32 1)316 store i32 %cvt, ptr addrspace(1) %out, align 4317 ret void318}319 320define amdgpu_ps void @test_cvt_scalef32_sr_fp8_f32_dst_sel_2(ptr addrspace(1) %out, float %src, i32 %seed, float %scale) {321; GFX950-LABEL: test_cvt_scalef32_sr_fp8_f32_dst_sel_2:322; GFX950: ; %bb.0:323; GFX950-NEXT: global_load_dword v5, v[0:1], off324; GFX950-NEXT: s_waitcnt vmcnt(0)325; GFX950-NEXT: v_cvt_scalef32_sr_fp8_f32 v5, v2, v3, v4 op_sel:[0,0,0,1]326; GFX950-NEXT: global_store_dword v[0:1], v5, off327; GFX950-NEXT: s_endpgm328 %old = load i32, ptr addrspace(1) %out, align 4329 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.fp8.f32(i32 %old, float %src, i32 %seed, float %scale, i32 2)330 store i32 %cvt, ptr addrspace(1) %out, align 4331 ret void332}333 334define amdgpu_ps void @test_cvt_scalef32_sr_fp8_f32_dst_sel_3(ptr addrspace(1) %out, float %src, i32 %seed, float %scale) {335; GFX950-LABEL: test_cvt_scalef32_sr_fp8_f32_dst_sel_3:336; GFX950: ; %bb.0:337; GFX950-NEXT: global_load_dword v5, v[0:1], off338; GFX950-NEXT: s_waitcnt vmcnt(0)339; GFX950-NEXT: v_cvt_scalef32_sr_fp8_f32 v5, v2, v3, v4 op_sel:[0,0,1,1]340; GFX950-NEXT: global_store_dword v[0:1], v5, off341; GFX950-NEXT: s_endpgm342 %old = load i32, ptr addrspace(1) %out, align 4343 %cvt = call i32 @llvm.amdgcn.cvt.scalef32.sr.fp8.f32(i32 %old, float %src, i32 %seed, float %scale, i32 3)344 store i32 %cvt, ptr addrspace(1) %out, align 4345 ret void346}347