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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-SDAG %s3; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-GISEL %s4 5declare <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.bf16(<8 x bfloat> %src, i32 %sr, float %scale)6declare <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.bf16(<8 x bfloat> %src, i32 %sr, float %scale)7declare <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.f16(<8 x half> %src, i32 %sr, float %scale)8declare <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.f16(<8 x half> %src, i32 %sr, float %scale)9declare <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.f32(<8 x float> %src, i32 %sr, float %scale)10declare <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.f32(<8 x float> %src, i32 %sr, float %scale)11declare i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.f32(<8 x float> %src, i32 %sr, float %scale)12declare i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.f16(<8 x half> %src, i32 %sr, float %scale)13declare i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.bf16(<8 x bfloat> %src, i32 %sr, float %scale)14 15define amdgpu_ps void @test_scalef32_sr_pk8_fp8_bf16_vv(<8 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {16; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_bf16_vv:17; GFX1250-SDAG: ; %bb.0:18; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 119; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp8_bf16 v[8:9], v[0:3], v4, v520; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off21; GFX1250-SDAG-NEXT: s_endpgm22;23; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp8_bf16_vv:24; GFX1250-GISEL: ; %bb.0:25; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 126; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp8_bf16 v[8:9], v[0:3], v4, v527; GFX1250-GISEL-NEXT: global_store_b64 v[6:7], v[8:9], off28; GFX1250-GISEL-NEXT: s_endpgm29 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.bf16(<8 x bfloat> %src, i32 %sr, float %scale)30 store <2 x i32> %cvt, ptr addrspace(1) %out, align 831 ret void32}33 34define amdgpu_ps void @test_scalef32_sr_pk8_fp8_bf16_sl(<8 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {35; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_bf16_sl:36; GFX1250-SDAG: ; %bb.0:37; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 138; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s139; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s340; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)41; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp8_bf16 v[6:7], v[2:5], s4, 0x42c8000042; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[6:7], off43; GFX1250-SDAG-NEXT: s_endpgm44;45; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp8_bf16_sl:46; GFX1250-GISEL: ; %bb.0:47; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 148; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s149; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s350; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)51; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp8_bf16 v[6:7], v[2:5], s4, 0x42c8000052; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off53; GFX1250-GISEL-NEXT: s_endpgm54 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.bf16(<8 x bfloat> %src, i32 %sr, float 100.0)55 store <2 x i32> %cvt, ptr addrspace(1) %out, align 856 ret void57}58 59define amdgpu_ps void @test_scalef32_sr_pk8_bf8_bf16_vv(<8 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {60; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_bf16_vv:61; GFX1250-SDAG: ; %bb.0:62; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 163; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_bf8_bf16 v[8:9], v[0:3], v4, v564; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off65; GFX1250-SDAG-NEXT: s_endpgm66;67; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_bf8_bf16_vv:68; GFX1250-GISEL: ; %bb.0:69; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 170; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_bf8_bf16 v[8:9], v[0:3], v4, v571; GFX1250-GISEL-NEXT: global_store_b64 v[6:7], v[8:9], off72; GFX1250-GISEL-NEXT: s_endpgm73 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.bf16(<8 x bfloat> %src, i32 %sr, float %scale)74 store <2 x i32> %cvt, ptr addrspace(1) %out, align 875 ret void76}77 78define amdgpu_ps void @test_scalef32_sr_pk8_bf8_bf16_sl(<8 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {79; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_bf16_sl:80; GFX1250-SDAG: ; %bb.0:81; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 182; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s183; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s384; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)85; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_bf8_bf16 v[6:7], v[2:5], s4, 0x42c8000086; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[6:7], off87; GFX1250-SDAG-NEXT: s_endpgm88;89; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_bf8_bf16_sl:90; GFX1250-GISEL: ; %bb.0:91; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 192; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s193; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s394; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)95; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_bf8_bf16 v[6:7], v[2:5], s4, 0x42c8000096; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off97; GFX1250-GISEL-NEXT: s_endpgm98 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.bf16(<8 x bfloat> %src, i32 %sr, float 100.0)99 store <2 x i32> %cvt, ptr addrspace(1) %out, align 8100 ret void101}102 103define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f16_vv(<8 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {104; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_f16_vv:105; GFX1250-SDAG: ; %bb.0:106; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1107; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp8_f16 v[8:9], v[0:3], v4, v5108; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off109; GFX1250-SDAG-NEXT: s_endpgm110;111; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp8_f16_vv:112; GFX1250-GISEL: ; %bb.0:113; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1114; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp8_f16 v[8:9], v[0:3], v4, v5115; GFX1250-GISEL-NEXT: global_store_b64 v[6:7], v[8:9], off116; GFX1250-GISEL-NEXT: s_endpgm117 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.f16(<8 x half> %src, i32 %sr, float %scale)118 store <2 x i32> %cvt, ptr addrspace(1) %out, align 8119 ret void120}121 122define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f16_sl(<8 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {123; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_f16_sl:124; GFX1250-SDAG: ; %bb.0:125; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1126; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1127; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3128; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)129; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp8_f16 v[6:7], v[2:5], s4, 0x42c80000130; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[6:7], off131; GFX1250-SDAG-NEXT: s_endpgm132;133; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp8_f16_sl:134; GFX1250-GISEL: ; %bb.0:135; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1136; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]137; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]138; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)139; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp8_f16 v[6:7], v[2:5], s4, 0x42c80000140; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off141; GFX1250-GISEL-NEXT: s_endpgm142 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.f16(<8 x half> %src, i32 %sr, float 100.0)143 store <2 x i32> %cvt, ptr addrspace(1) %out, align 8144 ret void145}146 147define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f16_vv(<8 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {148; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_f16_vv:149; GFX1250-SDAG: ; %bb.0:150; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1151; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_bf8_f16 v[8:9], v[0:3], v4, v5152; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off153; GFX1250-SDAG-NEXT: s_endpgm154;155; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_bf8_f16_vv:156; GFX1250-GISEL: ; %bb.0:157; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1158; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_bf8_f16 v[8:9], v[0:3], v4, v5159; GFX1250-GISEL-NEXT: global_store_b64 v[6:7], v[8:9], off160; GFX1250-GISEL-NEXT: s_endpgm161 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.f16(<8 x half> %src, i32 %sr, float %scale)162 store <2 x i32> %cvt, ptr addrspace(1) %out, align 8163 ret void164}165 166define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f16_sl(<8 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {167; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_f16_sl:168; GFX1250-SDAG: ; %bb.0:169; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1170; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1171; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3172; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)173; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_bf8_f16 v[6:7], v[2:5], s4, 0x42c80000174; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[6:7], off175; GFX1250-SDAG-NEXT: s_endpgm176;177; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_bf8_f16_sl:178; GFX1250-GISEL: ; %bb.0:179; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1180; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]181; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]182; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)183; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_bf8_f16 v[6:7], v[2:5], s4, 0x42c80000184; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off185; GFX1250-GISEL-NEXT: s_endpgm186 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.f16(<8 x half> %src, i32 %sr, float 100.0)187 store <2 x i32> %cvt, ptr addrspace(1) %out, align 8188 ret void189}190 191define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f32_vv(<8 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {192; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_f32_vv:193; GFX1250-SDAG: ; %bb.0:194; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1195; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_bf8_f32 v[12:13], v[0:7], v8, v9196; GFX1250-SDAG-NEXT: global_store_b64 v[10:11], v[12:13], off197; GFX1250-SDAG-NEXT: s_endpgm198;199; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_bf8_f32_vv:200; GFX1250-GISEL: ; %bb.0:201; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1202; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_bf8_f32 v[12:13], v[0:7], v8, v9203; GFX1250-GISEL-NEXT: global_store_b64 v[10:11], v[12:13], off204; GFX1250-GISEL-NEXT: s_endpgm205 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.f32(<8 x float> %src, i32 %sr, float %scale)206 store <2 x i32> %cvt, ptr addrspace(1) %out, align 8207 ret void208}209 210define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f32_sl(<8 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {211; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_f32_sl:212; GFX1250-SDAG: ; %bb.0:213; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1214; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1215; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3216; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5217; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7218; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)219; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_bf8_f32 v[10:11], v[2:9], s8, 0x42c80000220; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[10:11], off221; GFX1250-SDAG-NEXT: s_endpgm222;223; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_bf8_f32_sl:224; GFX1250-GISEL: ; %bb.0:225; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1226; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]227; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]228; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]229; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]230; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)231; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_bf8_f32 v[10:11], v[2:9], s8, 0x42c80000232; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[10:11], off233; GFX1250-GISEL-NEXT: s_endpgm234 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.f32(<8 x float> %src, i32 %sr, float 100.0)235 store <2 x i32> %cvt, ptr addrspace(1) %out, align 8236 ret void237}238 239define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f32_vv(<8 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {240; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_f32_vv:241; GFX1250-SDAG: ; %bb.0:242; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1243; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp8_f32 v[12:13], v[0:7], v8, v9244; GFX1250-SDAG-NEXT: global_store_b64 v[10:11], v[12:13], off245; GFX1250-SDAG-NEXT: s_endpgm246;247; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp8_f32_vv:248; GFX1250-GISEL: ; %bb.0:249; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1250; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp8_f32 v[12:13], v[0:7], v8, v9251; GFX1250-GISEL-NEXT: global_store_b64 v[10:11], v[12:13], off252; GFX1250-GISEL-NEXT: s_endpgm253 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.f32(<8 x float> %src, i32 %sr, float %scale)254 store <2 x i32> %cvt, ptr addrspace(1) %out, align 8255 ret void256}257 258define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f32_sl(<8 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {259; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_f32_sl:260; GFX1250-SDAG: ; %bb.0:261; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1262; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1263; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3264; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5265; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7266; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)267; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp8_f32 v[10:11], v[2:9], s8, 0x42c80000268; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[10:11], off269; GFX1250-SDAG-NEXT: s_endpgm270;271; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp8_f32_sl:272; GFX1250-GISEL: ; %bb.0:273; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1274; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]275; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]276; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]277; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]278; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)279; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp8_f32 v[10:11], v[2:9], s8, 0x42c80000280; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[10:11], off281; GFX1250-GISEL-NEXT: s_endpgm282 %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.f32(<8 x float> %src, i32 %sr, float 100.0)283 store <2 x i32> %cvt, ptr addrspace(1) %out, align 8284 ret void285}286 287define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f32_vv(<8 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {288; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_f32_vv:289; GFX1250-SDAG: ; %bb.0:290; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1291; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp4_f32 v12, v[0:7], v8, v9292; GFX1250-SDAG-NEXT: global_store_b32 v[10:11], v12, off293; GFX1250-SDAG-NEXT: s_endpgm294;295; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp4_f32_vv:296; GFX1250-GISEL: ; %bb.0:297; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1298; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp4_f32 v12, v[0:7], v8, v9299; GFX1250-GISEL-NEXT: global_store_b32 v[10:11], v12, off300; GFX1250-GISEL-NEXT: s_endpgm301 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.f32(<8 x float> %src, i32 %sr, float %scale)302 store i32 %cvt, ptr addrspace(1) %out, align 4303 ret void304}305 306define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f32_sl(<8 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {307; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_f32_sl:308; GFX1250-SDAG: ; %bb.0:309; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1310; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1311; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3312; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5313; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7314; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)315; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp4_f32 v10, v[2:9], s8, 0x42c80000316; GFX1250-SDAG-NEXT: global_store_b32 v[0:1], v10, off317; GFX1250-SDAG-NEXT: s_endpgm318;319; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp4_f32_sl:320; GFX1250-GISEL: ; %bb.0:321; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1322; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]323; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]324; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]325; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]326; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)327; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp4_f32 v10, v[2:9], s8, 0x42c80000328; GFX1250-GISEL-NEXT: global_store_b32 v[0:1], v10, off329; GFX1250-GISEL-NEXT: s_endpgm330 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.f32(<8 x float> %src, i32 %sr, float 100.0)331 store i32 %cvt, ptr addrspace(1) %out, align 4332 ret void333}334 335define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f16_vv(<8 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {336; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_f16_vv:337; GFX1250-SDAG: ; %bb.0:338; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1339; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp4_f16 v8, v[0:3], v4, v5340; GFX1250-SDAG-NEXT: global_store_b32 v[6:7], v8, off341; GFX1250-SDAG-NEXT: s_endpgm342;343; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp4_f16_vv:344; GFX1250-GISEL: ; %bb.0:345; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1346; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp4_f16 v8, v[0:3], v4, v5347; GFX1250-GISEL-NEXT: global_store_b32 v[6:7], v8, off348; GFX1250-GISEL-NEXT: s_endpgm349 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.f16(<8 x half> %src, i32 %sr, float %scale)350 store i32 %cvt, ptr addrspace(1) %out, align 4351 ret void352}353 354define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f16_sl(<8 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {355; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_f16_sl:356; GFX1250-SDAG: ; %bb.0:357; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1358; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1359; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3360; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)361; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp4_f16 v6, v[2:5], s4, 0x42c80000362; GFX1250-SDAG-NEXT: global_store_b32 v[0:1], v6, off363; GFX1250-SDAG-NEXT: s_endpgm364;365; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp4_f16_sl:366; GFX1250-GISEL: ; %bb.0:367; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1368; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]369; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]370; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)371; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp4_f16 v6, v[2:5], s4, 0x42c80000372; GFX1250-GISEL-NEXT: global_store_b32 v[0:1], v6, off373; GFX1250-GISEL-NEXT: s_endpgm374 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.f16(<8 x half> %src, i32 %sr, float 100.0)375 store i32 %cvt, ptr addrspace(1) %out, align 4376 ret void377}378 379define amdgpu_ps void @test_scalef32_sr_pk8_fp4_bf16_vv(<8 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {380; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_bf16_vv:381; GFX1250-SDAG: ; %bb.0:382; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1383; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp4_bf16 v8, v[0:3], v4, v5384; GFX1250-SDAG-NEXT: global_store_b32 v[6:7], v8, off385; GFX1250-SDAG-NEXT: s_endpgm386;387; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp4_bf16_vv:388; GFX1250-GISEL: ; %bb.0:389; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1390; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp4_bf16 v8, v[0:3], v4, v5391; GFX1250-GISEL-NEXT: global_store_b32 v[6:7], v8, off392; GFX1250-GISEL-NEXT: s_endpgm393 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.bf16(<8 x bfloat> %src, i32 %sr, float %scale)394 store i32 %cvt, ptr addrspace(1) %out, align 4395 ret void396}397 398define amdgpu_ps void @test_scalef32_sr_pk8_fp4_bf16_sl(<8 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {399; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_bf16_sl:400; GFX1250-SDAG: ; %bb.0:401; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1402; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1403; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3404; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)405; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp4_bf16 v6, v[2:5], s4, 0x42c80000406; GFX1250-SDAG-NEXT: global_store_b32 v[0:1], v6, off407; GFX1250-SDAG-NEXT: s_endpgm408;409; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp4_bf16_sl:410; GFX1250-GISEL: ; %bb.0:411; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1412; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1413; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3414; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)415; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp4_bf16 v6, v[2:5], s4, 0x42c80000416; GFX1250-GISEL-NEXT: global_store_b32 v[0:1], v6, off417; GFX1250-GISEL-NEXT: s_endpgm418 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.bf16(<8 x bfloat> %src, i32 %sr, float 100.0)419 store i32 %cvt, ptr addrspace(1) %out, align 4420 ret void421}422