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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950 %s3; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950 %s4 5declare i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f16(i32 %old, <2 x half> %src, i32 %seed, float %scale, i32 %dst_sel)6declare i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.bf16(i32 %old, <2 x bfloat> %src, i32 %seed, float %scale, i32 %dst_sel)7declare i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f32(i32 %old, <2 x float> %src, i32 %seed, float %scale, i32 %dst_sel)8 9define amdgpu_ps void @test_scalef32_sr_pk_fp4_f16_dst_sel_0(ptr addrspace(1) %out, <2 x half> %src, i32 %seed, float %scale) {10; GFX950-LABEL: test_scalef32_sr_pk_fp4_f16_dst_sel_0:11; GFX950: ; %bb.0:12; GFX950-NEXT: global_load_dword v5, v[0:1], off13; GFX950-NEXT: s_waitcnt vmcnt(0)14; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_f16 v6, v2, v3, v415; GFX950-NEXT: global_store_dword v[0:1], v6, off16; GFX950-NEXT: s_endpgm17 %old = load i32, ptr addrspace(1) %out, align 418 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f16(i32 %old, <2 x half> %src, i32 %seed, float %scale, i32 0)19 store i32 %cvt, ptr addrspace(1) %out, align 420 ret void21}22 23define amdgpu_ps void @test_scalef32_sr_pk_fp4_f16_dst_sel_1(ptr addrspace(1) %out, <2 x half> %src, i32 %seed, float %scale) {24; GFX950-LABEL: test_scalef32_sr_pk_fp4_f16_dst_sel_1:25; GFX950: ; %bb.0:26; GFX950-NEXT: global_load_dword v5, v[0:1], off27; GFX950-NEXT: s_waitcnt vmcnt(0)28; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_f16 v6, v2, v3, v4 op_sel:[0,0,1,0]29; GFX950-NEXT: global_store_dword v[0:1], v6, off30; GFX950-NEXT: s_endpgm31 %old = load i32, ptr addrspace(1) %out, align 432 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f16(i32 %old, <2 x half> %src, i32 %seed, float %scale, i32 1)33 store i32 %cvt, ptr addrspace(1) %out, align 434 ret void35}36 37define amdgpu_ps void @test_scalef32_sr_pk_fp4_f16_dst_sel_2(ptr addrspace(1) %out, <2 x half> %src, i32 %seed, float %scale) {38; GFX950-LABEL: test_scalef32_sr_pk_fp4_f16_dst_sel_2:39; GFX950: ; %bb.0:40; GFX950-NEXT: global_load_dword v5, v[0:1], off41; GFX950-NEXT: s_waitcnt vmcnt(0)42; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_f16 v6, v2, v3, v4 op_sel:[0,0,0,1]43; GFX950-NEXT: global_store_dword v[0:1], v6, off44; GFX950-NEXT: s_endpgm45 %old = load i32, ptr addrspace(1) %out, align 446 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f16(i32 %old, <2 x half> %src, i32 %seed, float %scale, i32 2)47 store i32 %cvt, ptr addrspace(1) %out, align 448 ret void49}50 51define amdgpu_ps void @test_scalef32_sr_pk_fp4_f16_dst_sel_3(ptr addrspace(1) %out, <2 x half> %src, i32 %seed, float %scale) {52; GFX950-LABEL: test_scalef32_sr_pk_fp4_f16_dst_sel_3:53; GFX950: ; %bb.0:54; GFX950-NEXT: global_load_dword v5, v[0:1], off55; GFX950-NEXT: s_waitcnt vmcnt(0)56; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_f16 v6, v2, v3, v4 op_sel:[0,0,1,1]57; GFX950-NEXT: global_store_dword v[0:1], v6, off58; GFX950-NEXT: s_endpgm59 %old = load i32, ptr addrspace(1) %out, align 460 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f16(i32 %old, <2 x half> %src, i32 %seed, float %scale, i32 3)61 store i32 %cvt, ptr addrspace(1) %out, align 462 ret void63}64 65define amdgpu_ps void @test_scalef32_sr_pk_fp4_bf16_dst_sel_0(ptr addrspace(1) %out, <2 x bfloat> %src, i32 %seed, float %scale) {66; GFX950-LABEL: test_scalef32_sr_pk_fp4_bf16_dst_sel_0:67; GFX950: ; %bb.0:68; GFX950-NEXT: global_load_dword v5, v[0:1], off69; GFX950-NEXT: s_waitcnt vmcnt(0)70; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_bf16 v6, v2, v3, v471; GFX950-NEXT: global_store_dword v[0:1], v6, off72; GFX950-NEXT: s_endpgm73 %old = load i32, ptr addrspace(1) %out, align 474 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.bf16(i32 %old, <2 x bfloat> %src, i32 %seed, float %scale, i32 0)75 store i32 %cvt, ptr addrspace(1) %out, align 476 ret void77}78 79define amdgpu_ps void @test_scalef32_sr_pk_fp4_bf16_dst_sel_1(ptr addrspace(1) %out, <2 x bfloat> %src, i32 %seed, float %scale) {80; GFX950-LABEL: test_scalef32_sr_pk_fp4_bf16_dst_sel_1:81; GFX950: ; %bb.0:82; GFX950-NEXT: global_load_dword v5, v[0:1], off83; GFX950-NEXT: s_waitcnt vmcnt(0)84; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_bf16 v6, v2, v3, v4 op_sel:[0,0,1,0]85; GFX950-NEXT: global_store_dword v[0:1], v6, off86; GFX950-NEXT: s_endpgm87 %old = load i32, ptr addrspace(1) %out, align 488 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.bf16(i32 %old, <2 x bfloat> %src, i32 %seed, float %scale, i32 1)89 store i32 %cvt, ptr addrspace(1) %out, align 490 ret void91}92 93define amdgpu_ps void @test_scalef32_sr_pk_fp4_bf16_dst_sel_2(ptr addrspace(1) %out, <2 x bfloat> %src, i32 %seed, float %scale) {94; GFX950-LABEL: test_scalef32_sr_pk_fp4_bf16_dst_sel_2:95; GFX950: ; %bb.0:96; GFX950-NEXT: global_load_dword v5, v[0:1], off97; GFX950-NEXT: s_waitcnt vmcnt(0)98; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_bf16 v6, v2, v3, v4 op_sel:[0,0,0,1]99; GFX950-NEXT: global_store_dword v[0:1], v6, off100; GFX950-NEXT: s_endpgm101 %old = load i32, ptr addrspace(1) %out, align 4102 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.bf16(i32 %old, <2 x bfloat> %src, i32 %seed, float %scale, i32 2)103 store i32 %cvt, ptr addrspace(1) %out, align 4104 ret void105}106 107define amdgpu_ps void @test_scalef32_sr_pk_fp4_bf16_dst_sel_3(ptr addrspace(1) %out, <2 x bfloat> %src, i32 %seed, float %scale) {108; GFX950-LABEL: test_scalef32_sr_pk_fp4_bf16_dst_sel_3:109; GFX950: ; %bb.0:110; GFX950-NEXT: global_load_dword v5, v[0:1], off111; GFX950-NEXT: s_waitcnt vmcnt(0)112; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_bf16 v6, v2, v3, v4 op_sel:[0,0,1,1]113; GFX950-NEXT: global_store_dword v[0:1], v6, off114; GFX950-NEXT: s_endpgm115 %old = load i32, ptr addrspace(1) %out, align 4116 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.bf16(i32 %old, <2 x bfloat> %src, i32 %seed, float %scale, i32 3)117 store i32 %cvt, ptr addrspace(1) %out, align 4118 ret void119}120 121define amdgpu_ps void @test_scalef32_sr_pk_fp4_f32_dst_sel_0(ptr addrspace(1) %out, <2 x float> %src, i32 %seed, float %scale) {122; GFX950-LABEL: test_scalef32_sr_pk_fp4_f32_dst_sel_0:123; GFX950: ; %bb.0:124; GFX950-NEXT: global_load_dword v6, v[0:1], off125; GFX950-NEXT: s_waitcnt vmcnt(0)126; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_f32 v7, v[2:3], v4, v5127; GFX950-NEXT: global_store_dword v[0:1], v7, off128; GFX950-NEXT: s_endpgm129 %old = load i32, ptr addrspace(1) %out, align 4130 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f32(i32 %old, <2 x float> %src, i32 %seed, float %scale, i32 0)131 store i32 %cvt, ptr addrspace(1) %out, align 4132 ret void133}134 135define amdgpu_ps void @test_scalef32_sr_pk_fp4_f32_dst_sel_1(ptr addrspace(1) %out, <2 x float> %src, i32 %seed, float %scale) {136; GFX950-LABEL: test_scalef32_sr_pk_fp4_f32_dst_sel_1:137; GFX950: ; %bb.0:138; GFX950-NEXT: global_load_dword v6, v[0:1], off139; GFX950-NEXT: s_waitcnt vmcnt(0)140; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_f32 v7, v[2:3], v4, v5 op_sel:[0,0,1,0]141; GFX950-NEXT: global_store_dword v[0:1], v7, off142; GFX950-NEXT: s_endpgm143 %old = load i32, ptr addrspace(1) %out, align 4144 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f32(i32 %old, <2 x float> %src, i32 %seed, float %scale, i32 1)145 store i32 %cvt, ptr addrspace(1) %out, align 4146 ret void147}148 149define amdgpu_ps void @test_scalef32_sr_pk_fp4_f32_dst_sel_2(ptr addrspace(1) %out, <2 x float> %src, i32 %seed, float %scale) {150; GFX950-LABEL: test_scalef32_sr_pk_fp4_f32_dst_sel_2:151; GFX950: ; %bb.0:152; GFX950-NEXT: global_load_dword v6, v[0:1], off153; GFX950-NEXT: s_waitcnt vmcnt(0)154; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_f32 v7, v[2:3], v4, v5 op_sel:[0,0,0,1]155; GFX950-NEXT: global_store_dword v[0:1], v7, off156; GFX950-NEXT: s_endpgm157 %old = load i32, ptr addrspace(1) %out, align 4158 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f32(i32 %old, <2 x float> %src, i32 %seed, float %scale, i32 2)159 store i32 %cvt, ptr addrspace(1) %out, align 4160 ret void161}162 163define amdgpu_ps void @test_scalef32_sr_pk_fp4_f32_dst_sel_3(ptr addrspace(1) %out, <2 x float> %src, i32 %seed, float %scale) {164; GFX950-LABEL: test_scalef32_sr_pk_fp4_f32_dst_sel_3:165; GFX950: ; %bb.0:166; GFX950-NEXT: global_load_dword v6, v[0:1], off167; GFX950-NEXT: s_waitcnt vmcnt(0)168; GFX950-NEXT: v_cvt_scalef32_sr_pk_fp4_f32 v7, v[2:3], v4, v5 op_sel:[0,0,1,1]169; GFX950-NEXT: global_store_dword v[0:1], v7, off170; GFX950-NEXT: s_endpgm171 %old = load i32, ptr addrspace(1) %out, align 4172 %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f32(i32 %old, <2 x float> %src, i32 %seed, float %scale, i32 3)173 store i32 %cvt, ptr addrspace(1) %out, align 4174 ret void175}176