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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950-SDAG %s3; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950-GISEL %s4 5declare <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.bf16(<32 x bfloat> %src, i32 %sr, float %scale)6declare <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.f16(<32 x half> %src, i32 %sr, float %scale)7declare <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.f32(<32 x float> %src, i32 %sr, float %scale)8declare <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.bf16(<32 x bfloat> %src, i32 %sr, float %scale)9declare <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.f16(<32 x half> %src, i32 %sr, float %scale)10declare <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.f32(<32 x float> %src, i32 %sr, float %scale)11 12define amdgpu_ps void @test_scalef32_sr_pk32_bf6_bf16_vv(<32 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {13; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_bf6_bf16_vv:14; GFX950-SDAG: ; %bb.0:15; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_bf6_bf16 v[20:25], v[0:15], v16, v1716; GFX950-SDAG-NEXT: global_store_dwordx2 v[18:19], v[24:25], off offset:1617; GFX950-SDAG-NEXT: global_store_dwordx4 v[18:19], v[20:23], off18; GFX950-SDAG-NEXT: s_endpgm19;20; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_bf6_bf16_vv:21; GFX950-GISEL: ; %bb.0:22; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_bf6_bf16 v[20:25], v[0:15], v16, v1723; GFX950-GISEL-NEXT: global_store_dwordx2 v[18:19], v[24:25], off offset:1624; GFX950-GISEL-NEXT: global_store_dwordx4 v[18:19], v[20:23], off25; GFX950-GISEL-NEXT: s_endpgm26 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.bf16(<32 x bfloat> %src, i32 %sr, float %scale)27 store <6 x i32> %cvt, ptr addrspace(1) %out, align 828 ret void29}30 31define amdgpu_ps void @test_scalef32_sr_pk32_bf6_bf16_sl(<32 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {32; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_bf6_bf16_sl:33; GFX950-SDAG: ; %bb.0:34; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s035; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s136; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s237; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s338; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s439; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s540; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s641; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s742; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s843; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s944; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s1045; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s1146; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s1247; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s1348; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s1449; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s1550; GFX950-SDAG-NEXT: v_mov_b32_e32 v24, 0x42c8000051; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_bf6_bf16 v[18:23], v[2:17], s16, v2452; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:1653; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[18:21], off54; GFX950-SDAG-NEXT: s_endpgm55;56; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_bf6_bf16_sl:57; GFX950-GISEL: ; %bb.0:58; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, s059; GFX950-GISEL-NEXT: v_mov_b32_e32 v3, s160; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, s261; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, s362; GFX950-GISEL-NEXT: v_mov_b32_e32 v6, s463; GFX950-GISEL-NEXT: v_mov_b32_e32 v7, s564; GFX950-GISEL-NEXT: v_mov_b32_e32 v8, s665; GFX950-GISEL-NEXT: v_mov_b32_e32 v9, s766; GFX950-GISEL-NEXT: v_mov_b32_e32 v10, s867; GFX950-GISEL-NEXT: v_mov_b32_e32 v11, s968; GFX950-GISEL-NEXT: v_mov_b32_e32 v12, s1069; GFX950-GISEL-NEXT: v_mov_b32_e32 v13, s1170; GFX950-GISEL-NEXT: v_mov_b32_e32 v14, s1271; GFX950-GISEL-NEXT: v_mov_b32_e32 v15, s1372; GFX950-GISEL-NEXT: v_mov_b32_e32 v16, s1473; GFX950-GISEL-NEXT: v_mov_b32_e32 v17, s1574; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c8000075; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_bf6_bf16 v[18:23], v[2:17], s16, v2476; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:1677; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off78; GFX950-GISEL-NEXT: s_endpgm79 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.bf16(<32 x bfloat> %src, i32 %sr, float 100.0)80 store <6 x i32> %cvt, ptr addrspace(1) %out, align 881 ret void82}83 84define amdgpu_ps void @test_scalef32_sr_pk32_bf6_f16_vv(<32 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {85; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_bf6_f16_vv:86; GFX950-SDAG: ; %bb.0:87; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_bf6_f16 v[20:25], v[0:15], v16, v1788; GFX950-SDAG-NEXT: global_store_dwordx2 v[18:19], v[24:25], off offset:1689; GFX950-SDAG-NEXT: global_store_dwordx4 v[18:19], v[20:23], off90; GFX950-SDAG-NEXT: s_endpgm91;92; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_bf6_f16_vv:93; GFX950-GISEL: ; %bb.0:94; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_bf6_f16 v[20:25], v[0:15], v16, v1795; GFX950-GISEL-NEXT: global_store_dwordx4 v[18:19], v[20:23], off96; GFX950-GISEL-NEXT: global_store_dwordx2 v[18:19], v[24:25], off offset:1697; GFX950-GISEL-NEXT: s_endpgm98 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.f16(<32 x half> %src, i32 %sr, float %scale)99 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8100 ret void101}102 103define amdgpu_ps void @test_scalef32_sr_pk32_bf6_f16_sl(<32 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {104; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_bf6_f16_sl:105; GFX950-SDAG: ; %bb.0:106; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0107; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1108; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2109; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3110; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4111; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5112; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6113; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7114; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8115; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9116; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10117; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11118; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12119; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13120; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14121; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15122; GFX950-SDAG-NEXT: v_mov_b32_e32 v24, 0x42c80000123; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_bf6_f16 v[18:23], v[2:17], s16, v24124; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16125; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[18:21], off126; GFX950-SDAG-NEXT: s_endpgm127;128; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_bf6_f16_sl:129; GFX950-GISEL: ; %bb.0:130; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]131; GFX950-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]132; GFX950-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]133; GFX950-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]134; GFX950-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]135; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]136; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]137; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]138; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000139; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_bf6_f16 v[18:23], v[2:17], s16, v24140; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off141; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16142; GFX950-GISEL-NEXT: s_endpgm143 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.f16(<32 x half> %src, i32 %sr, float 100.0)144 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8145 ret void146}147 148define amdgpu_ps void @test_scalef32_sr_pk32_fp6_bf16_vv(<32 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {149; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_fp6_bf16_vv:150; GFX950-SDAG: ; %bb.0:151; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_fp6_bf16 v[20:25], v[0:15], v16, v17152; GFX950-SDAG-NEXT: global_store_dwordx2 v[18:19], v[24:25], off offset:16153; GFX950-SDAG-NEXT: global_store_dwordx4 v[18:19], v[20:23], off154; GFX950-SDAG-NEXT: s_endpgm155;156; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_fp6_bf16_vv:157; GFX950-GISEL: ; %bb.0:158; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_fp6_bf16 v[20:25], v[0:15], v16, v17159; GFX950-GISEL-NEXT: global_store_dwordx2 v[18:19], v[24:25], off offset:16160; GFX950-GISEL-NEXT: global_store_dwordx4 v[18:19], v[20:23], off161; GFX950-GISEL-NEXT: s_endpgm162 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.bf16(<32 x bfloat> %src, i32 %sr, float %scale)163 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8164 ret void165}166 167define amdgpu_ps void @test_scalef32_sr_pk32_fp6_bf16_sl(<32 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {168; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_fp6_bf16_sl:169; GFX950-SDAG: ; %bb.0:170; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0171; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1172; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2173; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3174; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4175; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5176; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6177; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7178; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8179; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9180; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10181; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11182; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12183; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13184; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14185; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15186; GFX950-SDAG-NEXT: v_mov_b32_e32 v24, 0x42c80000187; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_fp6_bf16 v[18:23], v[2:17], s16, v24188; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16189; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[18:21], off190; GFX950-SDAG-NEXT: s_endpgm191;192; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_fp6_bf16_sl:193; GFX950-GISEL: ; %bb.0:194; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, s0195; GFX950-GISEL-NEXT: v_mov_b32_e32 v3, s1196; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, s2197; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, s3198; GFX950-GISEL-NEXT: v_mov_b32_e32 v6, s4199; GFX950-GISEL-NEXT: v_mov_b32_e32 v7, s5200; GFX950-GISEL-NEXT: v_mov_b32_e32 v8, s6201; GFX950-GISEL-NEXT: v_mov_b32_e32 v9, s7202; GFX950-GISEL-NEXT: v_mov_b32_e32 v10, s8203; GFX950-GISEL-NEXT: v_mov_b32_e32 v11, s9204; GFX950-GISEL-NEXT: v_mov_b32_e32 v12, s10205; GFX950-GISEL-NEXT: v_mov_b32_e32 v13, s11206; GFX950-GISEL-NEXT: v_mov_b32_e32 v14, s12207; GFX950-GISEL-NEXT: v_mov_b32_e32 v15, s13208; GFX950-GISEL-NEXT: v_mov_b32_e32 v16, s14209; GFX950-GISEL-NEXT: v_mov_b32_e32 v17, s15210; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000211; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_fp6_bf16 v[18:23], v[2:17], s16, v24212; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16213; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off214; GFX950-GISEL-NEXT: s_endpgm215 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.bf16(<32 x bfloat> %src, i32 %sr, float 100.0)216 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8217 ret void218}219 220define amdgpu_ps void @test_scalef32_sr_pk32_fp6_f16_vv(<32 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {221; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_fp6_f16_vv:222; GFX950-SDAG: ; %bb.0:223; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_fp6_f16 v[20:25], v[0:15], v16, v17224; GFX950-SDAG-NEXT: global_store_dwordx2 v[18:19], v[24:25], off offset:16225; GFX950-SDAG-NEXT: global_store_dwordx4 v[18:19], v[20:23], off226; GFX950-SDAG-NEXT: s_endpgm227;228; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_fp6_f16_vv:229; GFX950-GISEL: ; %bb.0:230; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_fp6_f16 v[20:25], v[0:15], v16, v17231; GFX950-GISEL-NEXT: global_store_dwordx4 v[18:19], v[20:23], off232; GFX950-GISEL-NEXT: global_store_dwordx2 v[18:19], v[24:25], off offset:16233; GFX950-GISEL-NEXT: s_endpgm234 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.f16(<32 x half> %src, i32 %sr, float %scale)235 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8236 ret void237}238 239define amdgpu_ps void @test_scalef32_sr_pk32_fp6_f16_sl(<32 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {240; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_fp6_f16_sl:241; GFX950-SDAG: ; %bb.0:242; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0243; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1244; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2245; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3246; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4247; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5248; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6249; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7250; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8251; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9252; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10253; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11254; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12255; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13256; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14257; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15258; GFX950-SDAG-NEXT: v_mov_b32_e32 v24, 0x42c80000259; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_fp6_f16 v[18:23], v[2:17], s16, v24260; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16261; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[18:21], off262; GFX950-SDAG-NEXT: s_endpgm263;264; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_fp6_f16_sl:265; GFX950-GISEL: ; %bb.0:266; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]267; GFX950-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]268; GFX950-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]269; GFX950-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]270; GFX950-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]271; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]272; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]273; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]274; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000275; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_fp6_f16 v[18:23], v[2:17], s16, v24276; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off277; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16278; GFX950-GISEL-NEXT: s_endpgm279 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.f16(<32 x half> %src, i32 %sr, float 100.0)280 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8281 ret void282}283 284define amdgpu_ps void @test_scalef32_sr_pk32_bf6_f32_vv(<32 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {285; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_bf6_f32_vv:286; GFX950-SDAG: ; %bb.0:287; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_bf6_f32 v[36:41], v[0:31], v32, v33288; GFX950-SDAG-NEXT: global_store_dwordx2 v[34:35], v[40:41], off offset:16289; GFX950-SDAG-NEXT: global_store_dwordx4 v[34:35], v[36:39], off290; GFX950-SDAG-NEXT: s_endpgm291;292; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_bf6_f32_vv:293; GFX950-GISEL: ; %bb.0:294; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_bf6_f32 v[36:41], v[0:31], v32, v33295; GFX950-GISEL-NEXT: global_store_dwordx4 v[34:35], v[36:39], off296; GFX950-GISEL-NEXT: global_store_dwordx2 v[34:35], v[40:41], off offset:16297; GFX950-GISEL-NEXT: s_endpgm298 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.f32(<32 x float> %src, i32 %sr, float %scale)299 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8300 ret void301}302 303define amdgpu_ps void @test_scalef32_sr_pk32_bf6_f32_sl(<32 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {304; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_bf6_f32_sl:305; GFX950-SDAG: ; %bb.0:306; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0307; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1308; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2309; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3310; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4311; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5312; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6313; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7314; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8315; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9316; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10317; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11318; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12319; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13320; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14321; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15322; GFX950-SDAG-NEXT: v_mov_b32_e32 v18, s16323; GFX950-SDAG-NEXT: v_mov_b32_e32 v19, s17324; GFX950-SDAG-NEXT: v_mov_b32_e32 v20, s18325; GFX950-SDAG-NEXT: v_mov_b32_e32 v21, s19326; GFX950-SDAG-NEXT: v_mov_b32_e32 v22, s20327; GFX950-SDAG-NEXT: v_mov_b32_e32 v23, s21328; GFX950-SDAG-NEXT: v_mov_b32_e32 v24, s22329; GFX950-SDAG-NEXT: v_mov_b32_e32 v25, s23330; GFX950-SDAG-NEXT: v_mov_b32_e32 v26, s24331; GFX950-SDAG-NEXT: v_mov_b32_e32 v27, s25332; GFX950-SDAG-NEXT: v_mov_b32_e32 v28, s26333; GFX950-SDAG-NEXT: v_mov_b32_e32 v29, s27334; GFX950-SDAG-NEXT: v_mov_b32_e32 v30, s28335; GFX950-SDAG-NEXT: v_mov_b32_e32 v31, s29336; GFX950-SDAG-NEXT: v_mov_b32_e32 v32, s30337; GFX950-SDAG-NEXT: v_mov_b32_e32 v33, s31338; GFX950-SDAG-NEXT: v_mov_b32_e32 v40, 0x42c80000339; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_bf6_f32 v[34:39], v[2:33], s32, v40340; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[38:39], off offset:16341; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[34:37], off342; GFX950-SDAG-NEXT: s_endpgm343;344; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_bf6_f32_sl:345; GFX950-GISEL: ; %bb.0:346; GFX950-GISEL-NEXT: v_mov_b64_e32 v[32:33], s[30:31]347; GFX950-GISEL-NEXT: v_mov_b64_e32 v[30:31], s[28:29]348; GFX950-GISEL-NEXT: v_mov_b64_e32 v[28:29], s[26:27]349; GFX950-GISEL-NEXT: v_mov_b64_e32 v[26:27], s[24:25]350; GFX950-GISEL-NEXT: v_mov_b64_e32 v[24:25], s[22:23]351; GFX950-GISEL-NEXT: v_mov_b64_e32 v[22:23], s[20:21]352; GFX950-GISEL-NEXT: v_mov_b64_e32 v[20:21], s[18:19]353; GFX950-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[16:17]354; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]355; GFX950-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]356; GFX950-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]357; GFX950-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]358; GFX950-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]359; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]360; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]361; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]362; GFX950-GISEL-NEXT: v_mov_b32_e32 v40, 0x42c80000363; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_bf6_f32 v[34:39], v[2:33], s32, v40364; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[34:37], off365; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[38:39], off offset:16366; GFX950-GISEL-NEXT: s_endpgm367 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.f32(<32 x float> %src, i32 %sr, float 100.0)368 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8369 ret void370}371 372define amdgpu_ps void @test_scalef32_sr_pk32_fp6_f32_vv(<32 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {373; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_fp6_f32_vv:374; GFX950-SDAG: ; %bb.0:375; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_fp6_f32 v[36:41], v[0:31], v32, v33376; GFX950-SDAG-NEXT: global_store_dwordx2 v[34:35], v[40:41], off offset:16377; GFX950-SDAG-NEXT: global_store_dwordx4 v[34:35], v[36:39], off378; GFX950-SDAG-NEXT: s_endpgm379;380; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_fp6_f32_vv:381; GFX950-GISEL: ; %bb.0:382; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_fp6_f32 v[36:41], v[0:31], v32, v33383; GFX950-GISEL-NEXT: global_store_dwordx4 v[34:35], v[36:39], off384; GFX950-GISEL-NEXT: global_store_dwordx2 v[34:35], v[40:41], off offset:16385; GFX950-GISEL-NEXT: s_endpgm386 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.f32(<32 x float> %src, i32 %sr, float %scale)387 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8388 ret void389}390 391define amdgpu_ps void @test_scalef32_sr_pk32_fp6_f32_sl(<32 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {392; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_fp6_f32_sl:393; GFX950-SDAG: ; %bb.0:394; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0395; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1396; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2397; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3398; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4399; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5400; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6401; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7402; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8403; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9404; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10405; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11406; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12407; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13408; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14409; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15410; GFX950-SDAG-NEXT: v_mov_b32_e32 v18, s16411; GFX950-SDAG-NEXT: v_mov_b32_e32 v19, s17412; GFX950-SDAG-NEXT: v_mov_b32_e32 v20, s18413; GFX950-SDAG-NEXT: v_mov_b32_e32 v21, s19414; GFX950-SDAG-NEXT: v_mov_b32_e32 v22, s20415; GFX950-SDAG-NEXT: v_mov_b32_e32 v23, s21416; GFX950-SDAG-NEXT: v_mov_b32_e32 v24, s22417; GFX950-SDAG-NEXT: v_mov_b32_e32 v25, s23418; GFX950-SDAG-NEXT: v_mov_b32_e32 v26, s24419; GFX950-SDAG-NEXT: v_mov_b32_e32 v27, s25420; GFX950-SDAG-NEXT: v_mov_b32_e32 v28, s26421; GFX950-SDAG-NEXT: v_mov_b32_e32 v29, s27422; GFX950-SDAG-NEXT: v_mov_b32_e32 v30, s28423; GFX950-SDAG-NEXT: v_mov_b32_e32 v31, s29424; GFX950-SDAG-NEXT: v_mov_b32_e32 v32, s30425; GFX950-SDAG-NEXT: v_mov_b32_e32 v33, s31426; GFX950-SDAG-NEXT: v_mov_b32_e32 v40, 0x42c80000427; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_fp6_f32 v[34:39], v[2:33], s32, v40428; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[38:39], off offset:16429; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[34:37], off430; GFX950-SDAG-NEXT: s_endpgm431;432; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_fp6_f32_sl:433; GFX950-GISEL: ; %bb.0:434; GFX950-GISEL-NEXT: v_mov_b64_e32 v[32:33], s[30:31]435; GFX950-GISEL-NEXT: v_mov_b64_e32 v[30:31], s[28:29]436; GFX950-GISEL-NEXT: v_mov_b64_e32 v[28:29], s[26:27]437; GFX950-GISEL-NEXT: v_mov_b64_e32 v[26:27], s[24:25]438; GFX950-GISEL-NEXT: v_mov_b64_e32 v[24:25], s[22:23]439; GFX950-GISEL-NEXT: v_mov_b64_e32 v[22:23], s[20:21]440; GFX950-GISEL-NEXT: v_mov_b64_e32 v[20:21], s[18:19]441; GFX950-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[16:17]442; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]443; GFX950-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]444; GFX950-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]445; GFX950-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]446; GFX950-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]447; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]448; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]449; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]450; GFX950-GISEL-NEXT: v_mov_b32_e32 v40, 0x42c80000451; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_fp6_f32 v[34:39], v[2:33], s32, v40452; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[34:37], off453; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[38:39], off offset:16454; GFX950-GISEL-NEXT: s_endpgm455 %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.f32(<32 x float> %src, i32 %sr, float 100.0)456 store <6 x i32> %cvt, ptr addrspace(1) %out, align 8457 ret void458}459