249 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s3; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s4 5declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.bf16(<16 x bfloat> %src, i32 %sr, float %scale)6declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f16(<16 x half> %src, i32 %sr, float %scale)7declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f32(<16 x float> %src, i32 %sr, float %scale)8declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.bf16(<16 x bfloat> %src, i32 %sr, float %scale)9declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f16(<16 x half> %src, i32 %sr, float %scale)10declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f32(<16 x float> %src, i32 %sr, float %scale)11 12define amdgpu_ps void @test_scalef32_sr_pk16_bf6_bf16_vv(<16 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {13; GFX1250-LABEL: test_scalef32_sr_pk16_bf6_bf16_vv:14; GFX1250: ; %bb.0:15; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 116; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_bf6_bf16 v[12:14], v[0:7], v8, v917; GFX1250-NEXT: global_store_b96 v[10:11], v[12:14], off18; GFX1250-NEXT: s_endpgm19 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.bf16(<16 x bfloat> %src, i32 %sr, float %scale)20 store <3 x i32> %cvt, ptr addrspace(1) %out, align 821 ret void22}23 24define amdgpu_ps void @test_scalef32_sr_pk16_bf6_bf16_sl(<16 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {25; GFX1250-LABEL: test_scalef32_sr_pk16_bf6_bf16_sl:26; GFX1250: ; %bb.0:27; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 128; GFX1250-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s129; GFX1250-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s330; GFX1250-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s531; GFX1250-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s732; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)33; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_bf6_bf16 v[10:12], v[2:9], s8, 0x42c8000034; GFX1250-NEXT: global_store_b96 v[0:1], v[10:12], off35; GFX1250-NEXT: s_endpgm36 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.bf16(<16 x bfloat> %src, i32 %sr, float 100.0)37 store <3 x i32> %cvt, ptr addrspace(1) %out, align 838 ret void39}40 41define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f16_vv(<16 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {42; GFX1250-LABEL: test_scalef32_sr_pk16_bf6_f16_vv:43; GFX1250: ; %bb.0:44; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 145; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_bf6_f16 v[12:14], v[0:7], v8, v946; GFX1250-NEXT: global_store_b96 v[10:11], v[12:14], off47; GFX1250-NEXT: s_endpgm48 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f16(<16 x half> %src, i32 %sr, float %scale)49 store <3 x i32> %cvt, ptr addrspace(1) %out, align 850 ret void51}52 53define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f16_sl(<16 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {54; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_bf6_f16_sl:55; GFX1250-SDAG: ; %bb.0:56; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 157; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s158; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s359; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s560; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s761; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)62; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk16_bf6_f16 v[10:12], v[2:9], s8, 0x42c8000063; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[10:12], off64; GFX1250-SDAG-NEXT: s_endpgm65;66; GFX1250-GISEL-LABEL: test_scalef32_sr_pk16_bf6_f16_sl:67; GFX1250-GISEL: ; %bb.0:68; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 169; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]70; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]71; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]72; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]73; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)74; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk16_bf6_f16 v[10:12], v[2:9], s8, 0x42c8000075; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[10:12], off76; GFX1250-GISEL-NEXT: s_endpgm77 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f16(<16 x half> %src, i32 %sr, float 100.0)78 store <3 x i32> %cvt, ptr addrspace(1) %out, align 879 ret void80}81 82define amdgpu_ps void @test_scalef32_sr_pk16_fp6_bf16_vv(<16 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {83; GFX1250-LABEL: test_scalef32_sr_pk16_fp6_bf16_vv:84; GFX1250: ; %bb.0:85; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 186; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_fp6_bf16 v[12:14], v[0:7], v8, v987; GFX1250-NEXT: global_store_b96 v[10:11], v[12:14], off88; GFX1250-NEXT: s_endpgm89 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.bf16(<16 x bfloat> %src, i32 %sr, float %scale)90 store <3 x i32> %cvt, ptr addrspace(1) %out, align 891 ret void92}93 94define amdgpu_ps void @test_scalef32_sr_pk16_fp6_bf16_sl(<16 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {95; GFX1250-LABEL: test_scalef32_sr_pk16_fp6_bf16_sl:96; GFX1250: ; %bb.0:97; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 198; GFX1250-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s199; GFX1250-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3100; GFX1250-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5101; GFX1250-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7102; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)103; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_fp6_bf16 v[10:12], v[2:9], s8, 0x42c80000104; GFX1250-NEXT: global_store_b96 v[0:1], v[10:12], off105; GFX1250-NEXT: s_endpgm106 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.bf16(<16 x bfloat> %src, i32 %sr, float 100.0)107 store <3 x i32> %cvt, ptr addrspace(1) %out, align 8108 ret void109}110 111define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f16_vv(<16 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {112; GFX1250-LABEL: test_scalef32_sr_pk16_fp6_f16_vv:113; GFX1250: ; %bb.0:114; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1115; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_fp6_f16 v[12:14], v[0:7], v8, v9116; GFX1250-NEXT: global_store_b96 v[10:11], v[12:14], off117; GFX1250-NEXT: s_endpgm118 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f16(<16 x half> %src, i32 %sr, float %scale)119 store <3 x i32> %cvt, ptr addrspace(1) %out, align 8120 ret void121}122 123define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f16_sl(<16 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {124; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_fp6_f16_sl:125; GFX1250-SDAG: ; %bb.0:126; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1127; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1128; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3129; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5130; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7131; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)132; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk16_fp6_f16 v[10:12], v[2:9], s8, 0x42c80000133; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[10:12], off134; GFX1250-SDAG-NEXT: s_endpgm135;136; GFX1250-GISEL-LABEL: test_scalef32_sr_pk16_fp6_f16_sl:137; GFX1250-GISEL: ; %bb.0:138; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1139; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]140; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]141; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]142; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]143; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)144; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk16_fp6_f16 v[10:12], v[2:9], s8, 0x42c80000145; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[10:12], off146; GFX1250-GISEL-NEXT: s_endpgm147 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f16(<16 x half> %src, i32 %sr, float 100.0)148 store <3 x i32> %cvt, ptr addrspace(1) %out, align 8149 ret void150}151 152define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f32_vv(<16 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {153; GFX1250-LABEL: test_scalef32_sr_pk16_bf6_f32_vv:154; GFX1250: ; %bb.0:155; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1156; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_bf6_f32 v[20:22], v[0:15], v16, v17157; GFX1250-NEXT: global_store_b96 v[18:19], v[20:22], off158; GFX1250-NEXT: s_endpgm159 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f32(<16 x float> %src, i32 %sr, float %scale)160 store <3 x i32> %cvt, ptr addrspace(1) %out, align 8161 ret void162}163 164define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f32_sl(<16 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {165; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_bf6_f32_sl:166; GFX1250-SDAG: ; %bb.0:167; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1168; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1169; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3170; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5171; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7172; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9173; GFX1250-SDAG-NEXT: v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s11174; GFX1250-SDAG-NEXT: v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, s13175; GFX1250-SDAG-NEXT: v_dual_mov_b32 v16, s14 :: v_dual_mov_b32 v17, s15176; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)177; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk16_bf6_f32 v[18:20], v[2:17], s16, 0x42c80000178; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[18:20], off179; GFX1250-SDAG-NEXT: s_endpgm180;181; GFX1250-GISEL-LABEL: test_scalef32_sr_pk16_bf6_f32_sl:182; GFX1250-GISEL: ; %bb.0:183; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1184; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]185; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]186; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]187; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]188; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]189; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]190; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]191; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]192; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)193; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk16_bf6_f32 v[18:20], v[2:17], s16, 0x42c80000194; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[18:20], off195; GFX1250-GISEL-NEXT: s_endpgm196 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f32(<16 x float> %src, i32 %sr, float 100.0)197 store <3 x i32> %cvt, ptr addrspace(1) %out, align 8198 ret void199}200 201define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f32_vv(<16 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {202; GFX1250-LABEL: test_scalef32_sr_pk16_fp6_f32_vv:203; GFX1250: ; %bb.0:204; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1205; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_fp6_f32 v[20:22], v[0:15], v16, v17206; GFX1250-NEXT: global_store_b96 v[18:19], v[20:22], off207; GFX1250-NEXT: s_endpgm208 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f32(<16 x float> %src, i32 %sr, float %scale)209 store <3 x i32> %cvt, ptr addrspace(1) %out, align 8210 ret void211}212 213define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f32_sl(<16 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {214; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_fp6_f32_sl:215; GFX1250-SDAG: ; %bb.0:216; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1217; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1218; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3219; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5220; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7221; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9222; GFX1250-SDAG-NEXT: v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s11223; GFX1250-SDAG-NEXT: v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, s13224; GFX1250-SDAG-NEXT: v_dual_mov_b32 v16, s14 :: v_dual_mov_b32 v17, s15225; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)226; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk16_fp6_f32 v[18:20], v[2:17], s16, 0x42c80000227; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[18:20], off228; GFX1250-SDAG-NEXT: s_endpgm229;230; GFX1250-GISEL-LABEL: test_scalef32_sr_pk16_fp6_f32_sl:231; GFX1250-GISEL: ; %bb.0:232; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1233; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]234; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]235; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]236; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]237; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]238; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]239; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]240; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]241; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)242; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk16_fp6_f32 v[18:20], v[2:17], s16, 0x42c80000243; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[18:20], off244; GFX1250-GISEL-NEXT: s_endpgm245 %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f32(<16 x float> %src, i32 %sr, float 100.0)246 store <3 x i32> %cvt, ptr addrspace(1) %out, align 8247 ret void248}249