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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 -o - %s | FileCheck -check-prefix=GFX950 %s3; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx950 -o - %s | FileCheck -check-prefix=GFX950 %s4 5declare <2 x half> @llvm.amdgcn.cvt.sr.f16.f32(<2 x half>, float, i32, i1)6declare <2 x bfloat> @llvm.amdgcn.cvt.sr.bf16.f32(<2 x bfloat>, float, i32, i1)7 8define amdgpu_ps void @test_cvt_sr_bf16_f32_word_sel_0(ptr addrspace(1) %out, float %src0, i32 %src1) {9; GFX950-LABEL: test_cvt_sr_bf16_f32_word_sel_0:10; GFX950: ; %bb.0:11; GFX950-NEXT: global_load_dword v4, v[0:1], off12; GFX950-NEXT: s_waitcnt vmcnt(0)13; GFX950-NEXT: v_cvt_sr_bf16_f32 v4, v2, v314; GFX950-NEXT: global_store_dword v[0:1], v4, off15; GFX950-NEXT: s_endpgm16 %old = load <2 x bfloat>, ptr addrspace(1) %out, align 417 %cvt = tail call <2 x bfloat> @llvm.amdgcn.cvt.sr.bf16.f32(<2 x bfloat> %old, float %src0, i32 %src1, i1 false)18 store <2 x bfloat> %cvt, ptr addrspace(1) %out, align 819 ret void20}21 22define amdgpu_ps void @test_cvt_sr_bf16_f32_word_sel_1(ptr addrspace(1) %out, float %src0, i32 %src1) {23; GFX950-LABEL: test_cvt_sr_bf16_f32_word_sel_1:24; GFX950: ; %bb.0:25; GFX950-NEXT: global_load_dword v4, v[0:1], off26; GFX950-NEXT: s_waitcnt vmcnt(0)27; GFX950-NEXT: v_cvt_sr_bf16_f32 v4, v2, v3 op_sel:[0,0,1]28; GFX950-NEXT: global_store_dword v[0:1], v4, off29; GFX950-NEXT: s_endpgm30 %old = load <2 x bfloat>, ptr addrspace(1) %out, align 431 %cvt = tail call <2 x bfloat> @llvm.amdgcn.cvt.sr.bf16.f32(<2 x bfloat> %old, float %src0, i32 %src1, i1 true)32 store <2 x bfloat> %cvt, ptr addrspace(1) %out, align 833 ret void34}35 36define amdgpu_ps void @test_cvt_sr_bf16_f32_fabs(ptr addrspace(1) %out, float %src0, i32 %src1) {37; GFX950-LABEL: test_cvt_sr_bf16_f32_fabs:38; GFX950: ; %bb.0:39; GFX950-NEXT: global_load_dword v4, v[0:1], off40; GFX950-NEXT: v_and_b32_e32 v2, 0x7fffffff, v241; GFX950-NEXT: s_waitcnt vmcnt(0)42; GFX950-NEXT: v_cvt_sr_bf16_f32 v4, v2, v343; GFX950-NEXT: global_store_dword v[0:1], v4, off44; GFX950-NEXT: s_endpgm45 %old = load <2 x bfloat>, ptr addrspace(1) %out, align 446 %src0.fabs = call float @llvm.fabs.f32(float %src0)47 %cvt = tail call <2 x bfloat> @llvm.amdgcn.cvt.sr.bf16.f32(<2 x bfloat> %old, float %src0.fabs, i32 %src1, i1 false)48 store <2 x bfloat> %cvt, ptr addrspace(1) %out, align 849 ret void50}51 52define amdgpu_ps void @test_cvt_sr_bf16_f32_fneg(ptr addrspace(1) %out, float %src0, i32 %src1) {53; GFX950-LABEL: test_cvt_sr_bf16_f32_fneg:54; GFX950: ; %bb.0:55; GFX950-NEXT: global_load_dword v4, v[0:1], off56; GFX950-NEXT: v_xor_b32_e32 v2, 0x80000000, v257; GFX950-NEXT: s_waitcnt vmcnt(0)58; GFX950-NEXT: v_cvt_sr_bf16_f32 v4, v2, v359; GFX950-NEXT: global_store_dword v[0:1], v4, off60; GFX950-NEXT: s_endpgm61 %old = load <2 x bfloat>, ptr addrspace(1) %out, align 462 %src0.fneg = fneg float %src063 %cvt = tail call <2 x bfloat> @llvm.amdgcn.cvt.sr.bf16.f32(<2 x bfloat> %old, float %src0.fneg, i32 %src1, i1 false)64 store <2 x bfloat> %cvt, ptr addrspace(1) %out, align 865 ret void66}67 68define amdgpu_ps void @test_cvt_sr_f16_f32_word_sel_0(ptr addrspace(1) %out, float %src0, i32 %src1) {69; GFX950-LABEL: test_cvt_sr_f16_f32_word_sel_0:70; GFX950: ; %bb.0:71; GFX950-NEXT: global_load_dword v4, v[0:1], off72; GFX950-NEXT: s_waitcnt vmcnt(0)73; GFX950-NEXT: v_cvt_sr_f16_f32 v4, v2, v374; GFX950-NEXT: global_store_dword v[0:1], v4, off75; GFX950-NEXT: s_endpgm76 %old = load <2 x half>, ptr addrspace(1) %out, align 477 %cvt = tail call <2 x half> @llvm.amdgcn.cvt.sr.f16.f32(<2 x half> %old, float %src0, i32 %src1, i1 false)78 store <2 x half> %cvt, ptr addrspace(1) %out, align 879 ret void80}81 82define amdgpu_ps void @test_cvt_sr_f16_f32_word_sel_1(ptr addrspace(1) %out, float %src0, i32 %src1) {83; GFX950-LABEL: test_cvt_sr_f16_f32_word_sel_1:84; GFX950: ; %bb.0:85; GFX950-NEXT: global_load_dword v4, v[0:1], off86; GFX950-NEXT: s_waitcnt vmcnt(0)87; GFX950-NEXT: v_cvt_sr_f16_f32 v4, v2, v3 op_sel:[0,0,1]88; GFX950-NEXT: global_store_dword v[0:1], v4, off89; GFX950-NEXT: s_endpgm90 %old = load <2 x half>, ptr addrspace(1) %out, align 491 %cvt = tail call <2 x half> @llvm.amdgcn.cvt.sr.f16.f32(<2 x half> %old, float %src0, i32 %src1, i1 true)92 store <2 x half> %cvt, ptr addrspace(1) %out, align 893 ret void94}95 96define amdgpu_ps void @test_cvt_sr_f16_f32_fabs(ptr addrspace(1) %out, float %src0, i32 %src1) {97; GFX950-LABEL: test_cvt_sr_f16_f32_fabs:98; GFX950: ; %bb.0:99; GFX950-NEXT: global_load_dword v4, v[0:1], off100; GFX950-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2101; GFX950-NEXT: s_waitcnt vmcnt(0)102; GFX950-NEXT: v_cvt_sr_f16_f32 v4, v2, v3103; GFX950-NEXT: global_store_dword v[0:1], v4, off104; GFX950-NEXT: s_endpgm105 %old = load <2 x half>, ptr addrspace(1) %out, align 4106 %src0.fabs = call float @llvm.fabs.f32(float %src0)107 %cvt = tail call <2 x half> @llvm.amdgcn.cvt.sr.f16.f32(<2 x half> %old, float %src0.fabs, i32 %src1, i1 false)108 store <2 x half> %cvt, ptr addrspace(1) %out, align 8109 ret void110}111 112define amdgpu_ps void @test_cvt_sr_f16_f32_fneg(ptr addrspace(1) %out, float %src0, i32 %src1) {113; GFX950-LABEL: test_cvt_sr_f16_f32_fneg:114; GFX950: ; %bb.0:115; GFX950-NEXT: global_load_dword v4, v[0:1], off116; GFX950-NEXT: v_xor_b32_e32 v2, 0x80000000, v2117; GFX950-NEXT: s_waitcnt vmcnt(0)118; GFX950-NEXT: v_cvt_sr_f16_f32 v4, v2, v3119; GFX950-NEXT: global_store_dword v[0:1], v4, off120; GFX950-NEXT: s_endpgm121 %old = load <2 x half>, ptr addrspace(1) %out, align 4122 %src0.fneg = fneg float %src0123 %cvt = tail call <2 x half> @llvm.amdgcn.cvt.sr.f16.f32(<2 x half> %old, float %src0.fneg, i32 %src1, i1 false)124 store <2 x half> %cvt, ptr addrspace(1) %out, align 8125 ret void126}127