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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GCN %s3; xUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GCN %s4 5; FIXME: GlobalISel does not work with bf166 7declare <2 x bfloat> @llvm.amdgcn.cvt.sr.pk.bf16.f32(float, float, i32) #08 9define amdgpu_ps float @cvt_sr_pk_bf16_f32_vvv(float %src0, float %src1, i32 %src2) #1 {10; GCN-LABEL: cvt_sr_pk_bf16_f32_vvv:11; GCN: ; %bb.0:12; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 113; GCN-NEXT: v_cvt_sr_pk_bf16_f32 v0, v0, v1, v214; GCN-NEXT: ; return to shader part epilog15 %cvt = call <2 x bfloat> @llvm.amdgcn.cvt.sr.pk.bf16.f32(float %src0, float %src1, i32 %src2) #016 %ret = bitcast <2 x bfloat> %cvt to float17 ret float %ret18}19 20define amdgpu_ps float @cvt_sr_pk_bf16_f32_sss(float inreg %src0, float inreg %src1, i32 inreg %src2) #1 {21; GCN-LABEL: cvt_sr_pk_bf16_f32_sss:22; GCN: ; %bb.0:23; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 124; GCN-NEXT: v_mov_b32_e32 v0, s225; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)26; GCN-NEXT: v_cvt_sr_pk_bf16_f32 v0, s0, s1, v027; GCN-NEXT: ; return to shader part epilog28 %cvt = call <2 x bfloat> @llvm.amdgcn.cvt.sr.pk.bf16.f32(float %src0, float %src1, i32 %src2) #029 %ret = bitcast <2 x bfloat> %cvt to float30 ret float %ret31}32 33define amdgpu_ps float @cvt_sr_pk_bf16_f32_vvi(float %src0, float %src1) #1 {34; GCN-LABEL: cvt_sr_pk_bf16_f32_vvi:35; GCN: ; %bb.0:36; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 137; GCN-NEXT: v_cvt_sr_pk_bf16_f32 v0, v0, v1, 0x1000238; GCN-NEXT: ; return to shader part epilog39 %cvt = call <2 x bfloat> @llvm.amdgcn.cvt.sr.pk.bf16.f32(float %src0, float %src1, i32 65538) #040 %ret = bitcast <2 x bfloat> %cvt to float41 ret float %ret42}43 44define amdgpu_ps float @cvt_sr_pk_bf16_f32_vvi_mods(float %src0, float %src1) #1 {45; GCN-LABEL: cvt_sr_pk_bf16_f32_vvi_mods:46; GCN: ; %bb.0:47; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 148; GCN-NEXT: v_cvt_sr_pk_bf16_f32 v0, -v0, |v1|, 149; GCN-NEXT: ; return to shader part epilog50 %s0 = fneg float %src051 %s1 = call float @llvm.fabs.f32(float %src1) #052 %cvt = call <2 x bfloat> @llvm.amdgcn.cvt.sr.pk.bf16.f32(float %s0, float %s1, i32 1) #053 %ret = bitcast <2 x bfloat> %cvt to float54 ret float %ret55}56 57define amdgpu_ps float @cvt_sr_pk_bf16_f32_ssi(float inreg %src0, float inreg %src1) #1 {58; GCN-LABEL: cvt_sr_pk_bf16_f32_ssi:59; GCN: ; %bb.0:60; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 161; GCN-NEXT: v_cvt_sr_pk_bf16_f32 v0, s0, s1, 162; GCN-NEXT: ; return to shader part epilog63 %cvt = call <2 x bfloat> @llvm.amdgcn.cvt.sr.pk.bf16.f32(float %src0, float %src1, i32 1) #064 %ret = bitcast <2 x bfloat> %cvt to float65 ret float %ret66}67 68declare float @llvm.fabs.f32(float) #069 70attributes #0 = { nounwind readnone }71attributes #1 = { nounwind }72