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1; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s2 3declare half @llvm.amdgcn.div.fixup.f16(half %a, half %b, half %c)4 5; GCN-LABEL: {{^}}div_fixup_f166; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]7; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]8; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]9; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]]10; GCN: buffer_store_short v[[R_F16]]11; GCN: s_endpgm12define amdgpu_kernel void @div_fixup_f16(13 ptr addrspace(1) %r,14 ptr addrspace(1) %a,15 ptr addrspace(1) %b,16 ptr addrspace(1) %c) {17entry:18 %a.val = load volatile half, ptr addrspace(1) %a19 %b.val = load volatile half, ptr addrspace(1) %b20 %c.val = load volatile half, ptr addrspace(1) %c21 %r.val = call half @llvm.amdgcn.div.fixup.f16(half %a.val, half %b.val, half %c.val)22 store half %r.val, ptr addrspace(1) %r23 ret void24}25 26; GCN-LABEL: {{^}}div_fixup_f16_imm_a27; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]28; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]29; VI: s_movk_i32 s[[A_F16:[0-9]+]], 0x4200{{$}}30; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], s[[A_F16]], v[[B_F16]], v[[C_F16]]31; GCN: buffer_store_short v[[R_F16]]32; GCN: s_endpgm33define amdgpu_kernel void @div_fixup_f16_imm_a(34 ptr addrspace(1) %r,35 ptr addrspace(1) %b,36 ptr addrspace(1) %c) {37entry:38 %b.val = load volatile half, ptr addrspace(1) %b39 %c.val = load volatile half, ptr addrspace(1) %c40 %r.val = call half @llvm.amdgcn.div.fixup.f16(half 3.0, half %b.val, half %c.val)41 store half %r.val, ptr addrspace(1) %r42 ret void43}44 45; GCN-LABEL: {{^}}div_fixup_f16_imm_b46; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]47; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]48; VI: s_movk_i32 s[[B_F16:[0-9]+]], 0x4200{{$}}49; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], s[[B_F16]], v[[C_F16]]50; GCN: buffer_store_short v[[R_F16]]51; GCN: s_endpgm52define amdgpu_kernel void @div_fixup_f16_imm_b(53 ptr addrspace(1) %r,54 ptr addrspace(1) %a,55 ptr addrspace(1) %c) {56entry:57 %a.val = load volatile half, ptr addrspace(1) %a58 %c.val = load volatile half, ptr addrspace(1) %c59 %r.val = call half @llvm.amdgcn.div.fixup.f16(half %a.val, half 3.0, half %c.val)60 store half %r.val, ptr addrspace(1) %r61 ret void62}63 64; GCN-LABEL: {{^}}div_fixup_f16_imm_c65; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]66; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]67; VI: s_movk_i32 s[[C_F16:[0-9]+]], 0x4200{{$}}68; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], s[[C_F16]]69; GCN: buffer_store_short v[[R_F16]]70; GCN: s_endpgm71define amdgpu_kernel void @div_fixup_f16_imm_c(72 ptr addrspace(1) %r,73 ptr addrspace(1) %a,74 ptr addrspace(1) %b) {75entry:76 %a.val = load volatile half, ptr addrspace(1) %a77 %b.val = load volatile half, ptr addrspace(1) %b78 %r.val = call half @llvm.amdgcn.div.fixup.f16(half %a.val, half %b.val, half 3.0)79 store half %r.val, ptr addrspace(1) %r80 ret void81}82 83; GCN-LABEL: {{^}}div_fixup_f16_imm_a_imm_b84; VI-DAG: s_movk_i32 [[AB_F16:s[0-9]+]], 0x4200{{$}}85; GCN-DAG: buffer_load_ushort v[[C_F16:[0-9]+]]86; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], [[AB_F16]], [[AB_F16]], v[[C_F16]]87; GCN: buffer_store_short v[[R_F16]]88; GCN: s_endpgm89define amdgpu_kernel void @div_fixup_f16_imm_a_imm_b(90 ptr addrspace(1) %r,91 ptr addrspace(1) %c) {92entry:93 %c.val = load volatile half, ptr addrspace(1) %c94 %r.val = call half @llvm.amdgcn.div.fixup.f16(half 3.0, half 3.0, half %c.val)95 store half %r.val, ptr addrspace(1) %r96 ret void97}98 99; GCN-LABEL: {{^}}div_fixup_f16_imm_b_imm_c100; VI-DAG: s_movk_i32 [[BC_F16:s[0-9]+]], 0x4200{{$}}101; GCN-DAG: buffer_load_ushort v[[A_F16:[0-9]+]]102; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], [[BC_F16]], [[BC_F16]]103; GCN: buffer_store_short v[[R_F16]]104; GCN: s_endpgm105define amdgpu_kernel void @div_fixup_f16_imm_b_imm_c(106 ptr addrspace(1) %r,107 ptr addrspace(1) %a) {108entry:109 %a.val = load half, ptr addrspace(1) %a110 %r.val = call half @llvm.amdgcn.div.fixup.f16(half %a.val, half 3.0, half 3.0)111 store half %r.val, ptr addrspace(1) %r112 ret void113}114 115; GCN-LABEL: {{^}}div_fixup_f16_imm_a_imm_c116; VI-DAG: s_movk_i32 [[AC_F16:s[0-9]+]], 0x4200{{$}}117; GCN-DAG: buffer_load_ushort v[[B_F16:[0-9]+]]118; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], [[AC_F16]], v[[B_F16]], [[AC_F16]]119; GCN: buffer_store_short v[[R_F16]]120; GCN: s_endpgm121define amdgpu_kernel void @div_fixup_f16_imm_a_imm_c(122 ptr addrspace(1) %r,123 ptr addrspace(1) %b) {124entry:125 %b.val = load half, ptr addrspace(1) %b126 %r.val = call half @llvm.amdgcn.div.fixup.f16(half 3.0, half %b.val, half 3.0)127 store half %r.val, ptr addrspace(1) %r128 ret void129}130