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1; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s2; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s3 4declare float @llvm.amdgcn.div.fixup.f32(float, float, float) nounwind readnone5declare double @llvm.amdgcn.div.fixup.f64(double, double, double) nounwind readnone6 7; GCN-LABEL: {{^}}test_div_fixup_f32:8; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x139; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1c10; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2511 12; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x4c13; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x7014; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9415 16; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]17; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]18; GCN: v_div_fixup_f32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]]19; GCN: buffer_store_dword [[RESULT]],20; GCN: s_endpgm21define amdgpu_kernel void @test_div_fixup_f32(ptr addrspace(1) %out, [8 x i32], float %a, [8 x i32], float %b, [8 x i32], float %c) nounwind {22 %result = call float @llvm.amdgcn.div.fixup.f32(float %a, float %b, float %c) nounwind readnone23 store float %result, ptr addrspace(1) %out, align 424 ret void25}26 27; GCN-LABEL: {{^}}test_div_fixup_f64:28; GCN: v_div_fixup_f6429define amdgpu_kernel void @test_div_fixup_f64(ptr addrspace(1) %out, double %a, double %b, double %c) nounwind {30 %result = call double @llvm.amdgcn.div.fixup.f64(double %a, double %b, double %c) nounwind readnone31 store double %result, ptr addrspace(1) %out, align 832 ret void33}34