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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s3; XUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s4 5; FIXME: Enable for VI.6 7declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone8declare float @llvm.amdgcn.div.fmas.f32(float, float, float, i1) nounwind readnone9declare double @llvm.amdgcn.div.fmas.f64(double, double, double, i1) nounwind readnone10 11define amdgpu_kernel void @test_div_fmas_f32(ptr addrspace(1) %out, [8 x i32], float %a, [8 x i32], float %b, [8 x i32], float %c, [8 x i32], i1 %d) nounwind {12; GCN-LABEL: test_div_fmas_f32:13; GCN:       ; %bb.0:14; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x915; GCN-NEXT:    s_load_dword s6, s[4:5], 0x1316; GCN-NEXT:    s_load_dword s2, s[4:5], 0x2e17; GCN-NEXT:    s_load_dword s7, s[4:5], 0x1c18; GCN-NEXT:    s_load_dword s4, s[4:5], 0x2519; GCN-NEXT:    s_mov_b32 s3, 0xf00020; GCN-NEXT:    s_waitcnt lgkmcnt(0)21; GCN-NEXT:    s_bitcmp1_b32 s2, 022; GCN-NEXT:    s_cselect_b64 vcc, -1, 023; GCN-NEXT:    s_mov_b32 s2, -124; GCN-NEXT:    v_mov_b32_e32 v0, s625; GCN-NEXT:    v_mov_b32_e32 v1, s726; GCN-NEXT:    v_mov_b32_e32 v2, s427; GCN-NEXT:    v_div_fmas_f32 v0, v0, v1, v228; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], 029; GCN-NEXT:    s_endpgm30  %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %d) nounwind readnone31  store float %result, ptr addrspace(1) %out, align 432  ret void33}34 35define amdgpu_kernel void @test_div_fmas_f32_inline_imm_0(ptr addrspace(1) %out, [8 x i32], float %a, [8 x i32], float %b, [8 x i32], float %c, [8 x i32], i1 %d) nounwind {36; GCN-LABEL: test_div_fmas_f32_inline_imm_0:37; GCN:       ; %bb.0:38; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x939; GCN-NEXT:    s_load_dword s2, s[4:5], 0x2e40; GCN-NEXT:    s_load_dword s6, s[4:5], 0x1c41; GCN-NEXT:    s_load_dword s4, s[4:5], 0x2542; GCN-NEXT:    s_mov_b32 s3, 0xf00043; GCN-NEXT:    s_waitcnt lgkmcnt(0)44; GCN-NEXT:    s_bitcmp1_b32 s2, 045; GCN-NEXT:    s_cselect_b64 vcc, -1, 046; GCN-NEXT:    s_mov_b32 s2, -147; GCN-NEXT:    v_mov_b32_e32 v0, s648; GCN-NEXT:    v_mov_b32_e32 v1, s449; GCN-NEXT:    v_div_fmas_f32 v0, 1.0, v0, v150; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], 051; GCN-NEXT:    s_endpgm52  %result = call float @llvm.amdgcn.div.fmas.f32(float 1.0, float %b, float %c, i1 %d) nounwind readnone53  store float %result, ptr addrspace(1) %out, align 454  ret void55}56 57define amdgpu_kernel void @test_div_fmas_f32_inline_imm_1(ptr addrspace(1) %out, float %a, float %b, float %c, [8 x i32], i1 %d) nounwind {58; GCN-LABEL: test_div_fmas_f32_inline_imm_1:59; GCN:       ; %bb.0:60; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x961; GCN-NEXT:    s_load_dword s2, s[4:5], 0x1662; GCN-NEXT:    s_load_dword s6, s[4:5], 0xb63; GCN-NEXT:    s_load_dword s4, s[4:5], 0xd64; GCN-NEXT:    s_mov_b32 s3, 0xf00065; GCN-NEXT:    s_waitcnt lgkmcnt(0)66; GCN-NEXT:    s_bitcmp1_b32 s2, 067; GCN-NEXT:    s_cselect_b64 vcc, -1, 068; GCN-NEXT:    s_mov_b32 s2, -169; GCN-NEXT:    v_mov_b32_e32 v0, s670; GCN-NEXT:    v_mov_b32_e32 v1, s471; GCN-NEXT:    v_div_fmas_f32 v0, v0, 1.0, v172; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], 073; GCN-NEXT:    s_endpgm74  %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float 1.0, float %c, i1 %d) nounwind readnone75  store float %result, ptr addrspace(1) %out, align 476  ret void77}78 79define amdgpu_kernel void @test_div_fmas_f32_inline_imm_2(ptr addrspace(1) %out, [8 x i32], float %a, [8 x i32], float %b, [8 x i32], float %c, [8 x i32], i1 %d) nounwind {80; GCN-LABEL: test_div_fmas_f32_inline_imm_2:81; GCN:       ; %bb.0:82; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x983; GCN-NEXT:    s_load_dword s2, s[4:5], 0x2e84; GCN-NEXT:    s_load_dword s6, s[4:5], 0x1385; GCN-NEXT:    s_load_dword s4, s[4:5], 0x1c86; GCN-NEXT:    s_mov_b32 s3, 0xf00087; GCN-NEXT:    s_waitcnt lgkmcnt(0)88; GCN-NEXT:    s_bitcmp1_b32 s2, 089; GCN-NEXT:    s_cselect_b64 vcc, -1, 090; GCN-NEXT:    s_mov_b32 s2, -191; GCN-NEXT:    v_mov_b32_e32 v0, s692; GCN-NEXT:    v_mov_b32_e32 v1, s493; GCN-NEXT:    v_div_fmas_f32 v0, v0, v1, 1.094; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], 095; GCN-NEXT:    s_endpgm96  %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float 1.0, i1 %d) nounwind readnone97  store float %result, ptr addrspace(1) %out, align 498  ret void99}100 101define amdgpu_kernel void @test_div_fmas_f64(ptr addrspace(1) %out, double %a, double %b, double %c, i1 %d) nounwind {102; GCN-LABEL: test_div_fmas_f64:103; GCN:       ; %bb.0:104; GCN-NEXT:    s_load_dword s8, s[4:5], 0x11105; GCN-NEXT:    s_load_dwordx8 s[0:7], s[4:5], 0x9106; GCN-NEXT:    s_mov_b32 s11, 0xf000107; GCN-NEXT:    s_waitcnt lgkmcnt(0)108; GCN-NEXT:    s_bitcmp1_b32 s8, 0109; GCN-NEXT:    s_cselect_b64 vcc, -1, 0110; GCN-NEXT:    s_mov_b32 s10, -1111; GCN-NEXT:    s_mov_b32 s8, s0112; GCN-NEXT:    s_mov_b32 s9, s1113; GCN-NEXT:    v_mov_b32_e32 v0, s2114; GCN-NEXT:    v_mov_b32_e32 v1, s3115; GCN-NEXT:    v_mov_b32_e32 v2, s4116; GCN-NEXT:    v_mov_b32_e32 v3, s5117; GCN-NEXT:    v_mov_b32_e32 v4, s6118; GCN-NEXT:    v_mov_b32_e32 v5, s7119; GCN-NEXT:    v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[4:5]120; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0121; GCN-NEXT:    s_endpgm122  %result = call double @llvm.amdgcn.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone123  store double %result, ptr addrspace(1) %out, align 8124  ret void125}126 127define amdgpu_kernel void @test_div_fmas_f32_cond_to_vcc(ptr addrspace(1) %out, float %a, float %b, float %c, i32 %i) nounwind {128; GCN-LABEL: test_div_fmas_f32_cond_to_vcc:129; GCN:       ; %bb.0:130; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0xb131; GCN-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x9132; GCN-NEXT:    s_mov_b32 s7, 0xf000133; GCN-NEXT:    s_waitcnt lgkmcnt(0)134; GCN-NEXT:    s_cmp_eq_u32 s3, 0135; GCN-NEXT:    s_cselect_b64 vcc, -1, 0136; GCN-NEXT:    s_mov_b32 s6, -1137; GCN-NEXT:    v_mov_b32_e32 v0, s0138; GCN-NEXT:    v_mov_b32_e32 v1, s1139; GCN-NEXT:    v_mov_b32_e32 v2, s2140; GCN-NEXT:    v_div_fmas_f32 v0, v0, v1, v2141; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0142; GCN-NEXT:    s_endpgm143  %cmp = icmp eq i32 %i, 0144  %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %cmp) nounwind readnone145  store float %result, ptr addrspace(1) %out, align 4146  ret void147}148 149define amdgpu_kernel void @test_div_fmas_f32_imm_false_cond_to_vcc(ptr addrspace(1) %out, float %a, float %b, float %c) nounwind {150; GCN-LABEL: test_div_fmas_f32_imm_false_cond_to_vcc:151; GCN:       ; %bb.0:152; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0xb153; GCN-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x9154; GCN-NEXT:    s_mov_b32 s7, 0xf000155; GCN-NEXT:    s_mov_b32 s6, -1156; GCN-NEXT:    s_waitcnt lgkmcnt(0)157; GCN-NEXT:    v_mov_b32_e32 v0, s0158; GCN-NEXT:    v_mov_b32_e32 v1, s1159; GCN-NEXT:    v_mov_b32_e32 v2, s2160; GCN-NEXT:    s_mov_b64 vcc, 0161; GCN-NEXT:    v_div_fmas_f32 v0, v0, v1, v2162; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0163; GCN-NEXT:    s_endpgm164  %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 false) nounwind readnone165  store float %result, ptr addrspace(1) %out, align 4166  ret void167}168 169define amdgpu_kernel void @test_div_fmas_f32_imm_true_cond_to_vcc(ptr addrspace(1) %out, float %a, float %b, float %c) nounwind {170; GCN-LABEL: test_div_fmas_f32_imm_true_cond_to_vcc:171; GCN:       ; %bb.0:172; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0xb173; GCN-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x9174; GCN-NEXT:    s_mov_b32 s7, 0xf000175; GCN-NEXT:    s_mov_b32 s6, -1176; GCN-NEXT:    s_waitcnt lgkmcnt(0)177; GCN-NEXT:    v_mov_b32_e32 v0, s0178; GCN-NEXT:    v_mov_b32_e32 v1, s1179; GCN-NEXT:    v_mov_b32_e32 v2, s2180; GCN-NEXT:    s_mov_b64 vcc, -1181; GCN-NEXT:    v_div_fmas_f32 v0, v0, v1, v2182; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0183; GCN-NEXT:    s_endpgm184  %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 true) nounwind readnone185  store float %result, ptr addrspace(1) %out, align 4186  ret void187}188 189define amdgpu_kernel void @test_div_fmas_f32_logical_cond_to_vcc(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %d) nounwind {190; GCN-LABEL: test_div_fmas_f32_logical_cond_to_vcc:191; GCN:       ; %bb.0:192; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9193; GCN-NEXT:    s_load_dword s8, s[4:5], 0xd194; GCN-NEXT:    s_mov_b32 s7, 0xf000195; GCN-NEXT:    s_mov_b32 s6, 0196; GCN-NEXT:    v_lshlrev_b32_e32 v1, 2, v0197; GCN-NEXT:    v_mov_b32_e32 v2, 0198; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0199; GCN-NEXT:    s_waitcnt lgkmcnt(0)200; GCN-NEXT:    s_mov_b64 s[4:5], s[2:3]201; GCN-NEXT:    buffer_load_dword v0, v[1:2], s[4:7], 0 addr64 glc202; GCN-NEXT:    s_waitcnt vmcnt(0)203; GCN-NEXT:    buffer_load_dword v3, v[1:2], s[4:7], 0 addr64 offset:4 glc204; GCN-NEXT:    s_waitcnt vmcnt(0)205; GCN-NEXT:    buffer_load_dword v1, v[1:2], s[4:7], 0 addr64 offset:8 glc206; GCN-NEXT:    s_waitcnt vmcnt(0)207; GCN-NEXT:    s_cmp_lg_u32 s8, 0208; GCN-NEXT:    s_cselect_b64 s[2:3], -1, 0209; GCN-NEXT:    s_and_b64 vcc, vcc, s[2:3]210; GCN-NEXT:    s_mov_b32 s2, -1211; GCN-NEXT:    s_mov_b32 s3, s7212; GCN-NEXT:    v_div_fmas_f32 v0, v0, v3, v1213; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:8214; GCN-NEXT:    s_endpgm215  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone216  %gep.a = getelementptr float, ptr addrspace(1) %in, i32 %tid217  %gep.b = getelementptr float, ptr addrspace(1) %gep.a, i32 1218  %gep.c = getelementptr float, ptr addrspace(1) %gep.a, i32 2219  %gep.out = getelementptr float, ptr addrspace(1) %out, i32 2220 221  %a = load volatile float, ptr addrspace(1) %gep.a222  %b = load volatile float, ptr addrspace(1) %gep.b223  %c = load volatile float, ptr addrspace(1) %gep.c224 225  %cmp0 = icmp eq i32 %tid, 0226  %cmp1 = icmp ne i32 %d, 0227  %and = and i1 %cmp0, %cmp1228 229  %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %and) nounwind readnone230  store float %result, ptr addrspace(1) %gep.out, align 4231  ret void232}233 234define amdgpu_kernel void @test_div_fmas_f32_i1_phi_vcc(ptr addrspace(1) %out, ptr addrspace(1) %in, ptr addrspace(1) %dummy) nounwind {235; GCN-LABEL: test_div_fmas_f32_i1_phi_vcc:236; GCN:       ; %bb.0: ; %entry237; GCN-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x9238; GCN-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd239; GCN-NEXT:    s_mov_b32 s3, 0xf000240; GCN-NEXT:    s_mov_b32 s2, 0241; GCN-NEXT:    v_lshlrev_b32_e32 v3, 2, v0242; GCN-NEXT:    v_mov_b32_e32 v4, 0243; GCN-NEXT:    s_waitcnt lgkmcnt(0)244; GCN-NEXT:    s_mov_b64 s[0:1], s[10:11]245; GCN-NEXT:    buffer_load_dwordx2 v[1:2], v[3:4], s[0:3], 0 addr64246; GCN-NEXT:    buffer_load_dword v3, v[3:4], s[0:3], 0 addr64 offset:8247; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v0248; GCN-NEXT:    s_mov_b64 vcc, 0249; GCN-NEXT:    s_and_saveexec_b64 s[10:11], s[0:1]250; GCN-NEXT:    s_cbranch_execz .LBB9_2251; GCN-NEXT:  ; %bb.1: ; %bb252; GCN-NEXT:    s_mov_b32 s6, -1253; GCN-NEXT:    s_mov_b32 s7, s3254; GCN-NEXT:    buffer_load_dword v0, off, s[4:7], 0255; GCN-NEXT:    s_waitcnt vmcnt(0)256; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0257; GCN-NEXT:    s_and_b64 vcc, vcc, exec258; GCN-NEXT:  .LBB9_2: ; %exit259; GCN-NEXT:    s_or_b64 exec, exec, s[10:11]260; GCN-NEXT:    s_waitcnt vmcnt(0)261; GCN-NEXT:    s_nop 0262; GCN-NEXT:    v_div_fmas_f32 v0, v1, v2, v3263; GCN-NEXT:    s_mov_b32 s10, -1264; GCN-NEXT:    s_mov_b32 s11, s3265; GCN-NEXT:    buffer_store_dword v0, off, s[8:11], 0 offset:8266; GCN-NEXT:    s_endpgm267entry:268  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone269  %gep.out = getelementptr float, ptr addrspace(1) %out, i32 2270  %gep.a = getelementptr float, ptr addrspace(1) %in, i32 %tid271  %gep.b = getelementptr float, ptr addrspace(1) %gep.a, i32 1272  %gep.c = getelementptr float, ptr addrspace(1) %gep.a, i32 2273 274  %a = load float, ptr addrspace(1) %gep.a275  %b = load float, ptr addrspace(1) %gep.b276  %c = load float, ptr addrspace(1) %gep.c277 278  %cmp0 = icmp eq i32 %tid, 0279  br i1 %cmp0, label %bb, label %exit280 281bb:282  %val = load i32, ptr addrspace(1) %dummy283  %cmp1 = icmp ne i32 %val, 0284  br label %exit285 286exit:287  %cond = phi i1 [false, %entry], [%cmp1, %bb]288  %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %cond) nounwind readnone289  store float %result, ptr addrspace(1) %gep.out, align 4290  ret void291}292;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:293; SI: {{.*}}294