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1; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=SI %s2 3declare i32 @llvm.amdgcn.workitem.id.x() #14declare { float, i1 } @llvm.amdgcn.div.scale.f32(float, float, i1) #15declare { double, i1 } @llvm.amdgcn.div.scale.f64(double, double, i1) #16declare float @llvm.fabs.f32(float) #17 8; SI-LABEL: {{^}}test_div_scale_f32_1:9; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr6410; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:411; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]12; SI: buffer_store_dword [[RESULT0]]13; SI: s_endpgm14define amdgpu_kernel void @test_div_scale_f32_1(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {15 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone16 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid17 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 118 19 %a = load volatile float, ptr addrspace(1) %gep.0, align 420 %b = load volatile float, ptr addrspace(1) %gep.1, align 421 22 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 false) nounwind readnone23 %result0 = extractvalue { float, i1 } %result, 024 store float %result0, ptr addrspace(1) %out, align 425 ret void26}27 28; SI-LABEL: {{^}}test_div_scale_f32_2:29; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr6430; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:431; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]32; SI: buffer_store_dword [[RESULT0]]33; SI: s_endpgm34define amdgpu_kernel void @test_div_scale_f32_2(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {35 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone36 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid37 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 138 39 %a = load volatile float, ptr addrspace(1) %gep.0, align 440 %b = load volatile float, ptr addrspace(1) %gep.1, align 441 42 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true) nounwind readnone43 %result0 = extractvalue { float, i1 } %result, 044 store float %result0, ptr addrspace(1) %out, align 445 ret void46}47 48; SI-LABEL: {{^}}test_div_scale_f64_1:49; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr6450; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:851; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]52; SI: buffer_store_dwordx2 [[RESULT0]]53; SI: s_endpgm54define amdgpu_kernel void @test_div_scale_f64_1(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %in) nounwind {55 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone56 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid57 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 158 59 %a = load volatile double, ptr addrspace(1) %gep.0, align 860 %b = load volatile double, ptr addrspace(1) %gep.1, align 861 62 %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 false) nounwind readnone63 %result0 = extractvalue { double, i1 } %result, 064 store double %result0, ptr addrspace(1) %out, align 865 ret void66}67 68; SI-LABEL: {{^}}test_div_scale_f64_2:69; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr6470; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:871; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]72; SI: buffer_store_dwordx2 [[RESULT0]]73; SI: s_endpgm74define amdgpu_kernel void @test_div_scale_f64_2(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %in) nounwind {75 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone76 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid77 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 178 79 %a = load volatile double, ptr addrspace(1) %gep.0, align 880 %b = load volatile double, ptr addrspace(1) %gep.1, align 881 82 %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 true) nounwind readnone83 %result0 = extractvalue { double, i1 } %result, 084 store double %result0, ptr addrspace(1) %out, align 885 ret void86}87 88; SI-LABEL: {{^}}test_div_scale_f32_scalar_num_1:89; SI-DAG: buffer_load_dword [[B:v[0-9]+]]90; SI-DAG: s_load_dword [[A:s[0-9]+]]91; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]92; SI: buffer_store_dword [[RESULT0]]93; SI: s_endpgm94define amdgpu_kernel void @test_div_scale_f32_scalar_num_1(ptr addrspace(1) %out, ptr addrspace(1) %in, float %a) nounwind {95 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone96 %gep = getelementptr float, ptr addrspace(1) %in, i32 %tid97 98 %b = load float, ptr addrspace(1) %gep, align 499 100 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 false) nounwind readnone101 %result0 = extractvalue { float, i1 } %result, 0102 store float %result0, ptr addrspace(1) %out, align 4103 ret void104}105 106; SI-LABEL: {{^}}test_div_scale_f32_scalar_num_2:107; SI-DAG: buffer_load_dword [[B:v[0-9]+]]108; SI-DAG: s_load_dword [[A:s[0-9]+]]109; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]110; SI: buffer_store_dword [[RESULT0]]111; SI: s_endpgm112define amdgpu_kernel void @test_div_scale_f32_scalar_num_2(ptr addrspace(1) %out, ptr addrspace(1) %in, float %a) nounwind {113 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone114 %gep = getelementptr float, ptr addrspace(1) %in, i32 %tid115 116 %b = load float, ptr addrspace(1) %gep, align 4117 118 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true) nounwind readnone119 %result0 = extractvalue { float, i1 } %result, 0120 store float %result0, ptr addrspace(1) %out, align 4121 ret void122}123 124; SI-LABEL: {{^}}test_div_scale_f32_scalar_den_1:125; SI-DAG: buffer_load_dword [[A:v[0-9]+]]126; SI-DAG: s_load_dword [[B:s[0-9]+]]127; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]128; SI: buffer_store_dword [[RESULT0]]129; SI: s_endpgm130define amdgpu_kernel void @test_div_scale_f32_scalar_den_1(ptr addrspace(1) %out, ptr addrspace(1) %in, float %b) nounwind {131 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone132 %gep = getelementptr float, ptr addrspace(1) %in, i32 %tid133 134 %a = load float, ptr addrspace(1) %gep, align 4135 136 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 false) nounwind readnone137 %result0 = extractvalue { float, i1 } %result, 0138 store float %result0, ptr addrspace(1) %out, align 4139 ret void140}141 142; SI-LABEL: {{^}}test_div_scale_f32_scalar_den_2:143; SI-DAG: buffer_load_dword [[A:v[0-9]+]]144; SI-DAG: s_load_dword [[B:s[0-9]+]]145; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]146; SI: buffer_store_dword [[RESULT0]]147; SI: s_endpgm148define amdgpu_kernel void @test_div_scale_f32_scalar_den_2(ptr addrspace(1) %out, ptr addrspace(1) %in, float %b) nounwind {149 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone150 %gep = getelementptr float, ptr addrspace(1) %in, i32 %tid151 152 %a = load float, ptr addrspace(1) %gep, align 4153 154 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true) nounwind readnone155 %result0 = extractvalue { float, i1 } %result, 0156 store float %result0, ptr addrspace(1) %out, align 4157 ret void158}159 160; SI-LABEL: {{^}}test_div_scale_f64_scalar_num_1:161; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]]162; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd163; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]164; SI: buffer_store_dwordx2 [[RESULT0]]165; SI: s_endpgm166define amdgpu_kernel void @test_div_scale_f64_scalar_num_1(ptr addrspace(1) %out, ptr addrspace(1) %in, double %a) nounwind {167 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone168 %gep = getelementptr double, ptr addrspace(1) %in, i32 %tid169 170 %b = load double, ptr addrspace(1) %gep, align 8171 172 %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 false) nounwind readnone173 %result0 = extractvalue { double, i1 } %result, 0174 store double %result0, ptr addrspace(1) %out, align 8175 ret void176}177 178; SI-LABEL: {{^}}test_div_scale_f64_scalar_num_2:179; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd180; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]]181; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]182; SI: buffer_store_dwordx2 [[RESULT0]]183; SI: s_endpgm184define amdgpu_kernel void @test_div_scale_f64_scalar_num_2(ptr addrspace(1) %out, ptr addrspace(1) %in, double %a) nounwind {185 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone186 %gep = getelementptr double, ptr addrspace(1) %in, i32 %tid187 188 %b = load double, ptr addrspace(1) %gep, align 8189 190 %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 true) nounwind readnone191 %result0 = extractvalue { double, i1 } %result, 0192 store double %result0, ptr addrspace(1) %out, align 8193 ret void194}195 196; SI-LABEL: {{^}}test_div_scale_f64_scalar_den_1:197; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]]198; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd199; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]200; SI: buffer_store_dwordx2 [[RESULT0]]201; SI: s_endpgm202define amdgpu_kernel void @test_div_scale_f64_scalar_den_1(ptr addrspace(1) %out, ptr addrspace(1) %in, double %b) nounwind {203 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone204 %gep = getelementptr double, ptr addrspace(1) %in, i32 %tid205 206 %a = load double, ptr addrspace(1) %gep, align 8207 208 %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 false) nounwind readnone209 %result0 = extractvalue { double, i1 } %result, 0210 store double %result0, ptr addrspace(1) %out, align 8211 ret void212}213 214; SI-LABEL: {{^}}test_div_scale_f64_scalar_den_2:215; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]]216; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd217; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]218; SI: buffer_store_dwordx2 [[RESULT0]]219; SI: s_endpgm220define amdgpu_kernel void @test_div_scale_f64_scalar_den_2(ptr addrspace(1) %out, ptr addrspace(1) %in, double %b) nounwind {221 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone222 %gep = getelementptr double, ptr addrspace(1) %in, i32 %tid223 224 %a = load double, ptr addrspace(1) %gep, align 8225 226 %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 true) nounwind readnone227 %result0 = extractvalue { double, i1 } %result, 0228 store double %result0, ptr addrspace(1) %out, align 8229 ret void230}231 232; SI-LABEL: {{^}}test_div_scale_f32_all_scalar_1:233; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0x13234; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0x1c235; SI: v_mov_b32_e32 [[VA:v[0-9]+]], [[A]]236; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[VA]]237; SI: buffer_store_dword [[RESULT0]]238; SI: s_endpgm239define amdgpu_kernel void @test_div_scale_f32_all_scalar_1(ptr addrspace(1) %out, [8 x i32], float %a, [8 x i32], float %b) nounwind {240 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 false) nounwind readnone241 %result0 = extractvalue { float, i1 } %result, 0242 store float %result0, ptr addrspace(1) %out, align 4243 ret void244}245 246; SI-LABEL: {{^}}test_div_scale_f32_all_scalar_2:247; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0x13248; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0x1c249; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[B]]250; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[VB]], [[A]]251; SI: buffer_store_dword [[RESULT0]]252; SI: s_endpgm253define amdgpu_kernel void @test_div_scale_f32_all_scalar_2(ptr addrspace(1) %out, [8 x i32], float %a, [8 x i32], float %b) nounwind {254 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true) nounwind readnone255 %result0 = extractvalue { float, i1 } %result, 0256 store float %result0, ptr addrspace(1) %out, align 4257 ret void258}259 260; SI-LABEL: {{^}}test_div_scale_f64_all_scalar_1:261; SI-DAG: s_load_dwordx2 s[[[A_LO:[0-9]+]]:[[A_HI:[0-9]+]]], {{s\[[0-9]+:[0-9]+\]}}, 0x13262; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x1d263; SI-DAG: v_mov_b32_e32 v[[VA_LO:[0-9]+]], s[[A_LO]]264; SI-DAG: v_mov_b32_e32 v[[VA_HI:[0-9]+]], s[[A_HI]]265; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], v[[[VA_LO]]:[[VA_HI]]]266; SI: buffer_store_dwordx2 [[RESULT0]]267; SI: s_endpgm268define amdgpu_kernel void @test_div_scale_f64_all_scalar_1(ptr addrspace(1) %out, [8 x i32], double %a, [8 x i32], double %b) nounwind {269 %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 false) nounwind readnone270 %result0 = extractvalue { double, i1 } %result, 0271 store double %result0, ptr addrspace(1) %out, align 8272 ret void273}274 275; SI-LABEL: {{^}}test_div_scale_f64_all_scalar_2:276; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x13277; SI-DAG: s_load_dwordx2 s[[[B_LO:[0-9]+]]:[[B_HI:[0-9]+]]], {{s\[[0-9]+:[0-9]+\]}}, 0x1d278; SI-DAG: v_mov_b32_e32 v[[VB_LO:[0-9]+]], s[[B_LO]]279; SI-DAG: v_mov_b32_e32 v[[VB_HI:[0-9]+]], s[[B_HI]]280; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], v[[[VB_LO]]:[[VB_HI]]], [[A]]281; SI: buffer_store_dwordx2 [[RESULT0]]282; SI: s_endpgm283define amdgpu_kernel void @test_div_scale_f64_all_scalar_2(ptr addrspace(1) %out, [8 x i32], double %a, [8 x i32], double %b) nounwind {284 %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 true) nounwind readnone285 %result0 = extractvalue { double, i1 } %result, 0286 store double %result0, ptr addrspace(1) %out, align 8287 ret void288}289 290; SI-LABEL: {{^}}test_div_scale_f32_inline_imm_num:291; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}292; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[A]], 1.0293; SI: buffer_store_dword [[RESULT0]]294; SI: s_endpgm295define amdgpu_kernel void @test_div_scale_f32_inline_imm_num(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {296 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone297 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid298 %a = load float, ptr addrspace(1) %gep.0, align 4299 300 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float 1.0, float %a, i1 false) nounwind readnone301 %result0 = extractvalue { float, i1 } %result, 0302 store float %result0, ptr addrspace(1) %out, align 4303 ret void304}305 306; SI-LABEL: {{^}}test_div_scale_f32_inline_imm_den:307; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}308; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], 2.0, 2.0, [[A]]309; SI: buffer_store_dword [[RESULT0]]310; SI: s_endpgm311define amdgpu_kernel void @test_div_scale_f32_inline_imm_den(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {312 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone313 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid314 %a = load float, ptr addrspace(1) %gep.0, align 4315 316 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float 2.0, i1 false) nounwind readnone317 %result0 = extractvalue { float, i1 } %result, 0318 store float %result0, ptr addrspace(1) %out, align 4319 ret void320}321 322; SI-LABEL: {{^}}test_div_scale_f32_fneg_num:323; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64324; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4325; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], -[[A]]326; SI: buffer_store_dword [[RESULT0]]327; SI: s_endpgm328define amdgpu_kernel void @test_div_scale_f32_fneg_num(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {329 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone330 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid331 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1332 333 %a = load volatile float, ptr addrspace(1) %gep.0, align 4334 %b = load volatile float, ptr addrspace(1) %gep.1, align 4335 336 %a.fneg = fneg float %a337 338 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a.fneg, float %b, i1 false) nounwind readnone339 %result0 = extractvalue { float, i1 } %result, 0340 store float %result0, ptr addrspace(1) %out, align 4341 ret void342}343 344; SI-LABEL: {{^}}test_div_scale_f32_fabs_num:345; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64346; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4347; SI: v_and_b32_e32 [[ABS_A:v[0-9]+]], 0x7fffffff, [[A]]348; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[ABS_A]]349; SI: buffer_store_dword [[RESULT0]]350; SI: s_endpgm351define amdgpu_kernel void @test_div_scale_f32_fabs_num(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {352 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone353 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid354 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1355 356 %a = load volatile float, ptr addrspace(1) %gep.0, align 4357 %b = load volatile float, ptr addrspace(1) %gep.1, align 4358 359 %a.fabs = call float @llvm.fabs.f32(float %a) nounwind readnone360 361 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a.fabs, float %b, i1 false) nounwind readnone362 %result0 = extractvalue { float, i1 } %result, 0363 store float %result0, ptr addrspace(1) %out, align 4364 ret void365}366 367; SI-LABEL: {{^}}test_div_scale_f32_fneg_den:368; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64369; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4370; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], -[[B]], -[[B]], [[A]]371; SI: buffer_store_dword [[RESULT0]]372; SI: s_endpgm373define amdgpu_kernel void @test_div_scale_f32_fneg_den(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {374 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone375 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid376 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1377 378 %a = load volatile float, ptr addrspace(1) %gep.0, align 4379 %b = load volatile float, ptr addrspace(1) %gep.1, align 4380 381 %b.fneg = fneg float %b382 383 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b.fneg, i1 false) nounwind readnone384 %result0 = extractvalue { float, i1 } %result, 0385 store float %result0, ptr addrspace(1) %out, align 4386 ret void387}388 389; SI-LABEL: {{^}}test_div_scale_f32_fabs_den:390; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64391; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4392; SI: v_and_b32_e32 [[ABS_B:v[0-9]+]], 0x7fffffff, [[B]]393; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[ABS_B]], [[ABS_B]], [[A]]394; SI: buffer_store_dword [[RESULT0]]395; SI: s_endpgm396define amdgpu_kernel void @test_div_scale_f32_fabs_den(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {397 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone398 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid399 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1400 401 %a = load volatile float, ptr addrspace(1) %gep.0, align 4402 %b = load volatile float, ptr addrspace(1) %gep.1, align 4403 404 %b.fabs = call float @llvm.fabs.f32(float %b) nounwind readnone405 406 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b.fabs, i1 false) nounwind readnone407 %result0 = extractvalue { float, i1 } %result, 0408 store float %result0, ptr addrspace(1) %out, align 4409 ret void410}411 412; SI-LABEL: {{^}}test_div_scale_f32_val_undef_val:413; SI: s_mov_b32 [[K:s[0-9]+]], 0x41000000414; SI: v_div_scale_f32 v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, [[K]], v{{[0-9]+}}, [[K]]415define amdgpu_kernel void @test_div_scale_f32_val_undef_val(ptr addrspace(1) %out) #0 {416 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float 8.0, float poison, i1 false)417 %result0 = extractvalue { float, i1 } %result, 0418 store float %result0, ptr addrspace(1) %out, align 4419 ret void420}421 422; SI-LABEL: {{^}}test_div_scale_f32_undef_val_val:423; SI: s_mov_b32 [[K:s[0-9]+]], 0x41000000424; SI: v_div_scale_f32 v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, [[K]], [[K]], v{{[0-9]+}}425define amdgpu_kernel void @test_div_scale_f32_undef_val_val(ptr addrspace(1) %out) #0 {426 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float poison, float 8.0, i1 false)427 %result0 = extractvalue { float, i1 } %result, 0428 store float %result0, ptr addrspace(1) %out, align 4429 ret void430}431 432; SI-LABEL: {{^}}test_div_scale_f32_undef_undef_val:433; SI-NOT: v0434; SI: v_div_scale_f32 v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s0, s0, v0435define amdgpu_kernel void @test_div_scale_f32_undef_undef_val(ptr addrspace(1) %out) #0 {436 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float poison, float poison, i1 false)437 %result0 = extractvalue { float, i1 } %result, 0438 store float %result0, ptr addrspace(1) %out, align 4439 ret void440}441 442; SI-LABEL: {{^}}test_div_scale_f64_val_undef_val:443; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}}444; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0x40200000445; SI: v_div_scale_f64 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s[[[K_LO]]:[[K_HI]]], v[0:1], s[[[K_LO]]:[[K_HI]]]446define amdgpu_kernel void @test_div_scale_f64_val_undef_val(ptr addrspace(1) %out) #0 {447 %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double 8.0, double poison, i1 false)448 %result0 = extractvalue { double, i1 } %result, 0449 store double %result0, ptr addrspace(1) %out, align 8450 ret void451}452 453attributes #0 = { nounwind }454attributes #1 = { nounwind readnone speculatable }455