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1; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,NOTGFX9 %s2; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,NOTGFX9 %s3; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefixes=GCN,CIPLUS,NOTGFX9 %s4; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefixes=GCN,CIPLUS,NOTGFX9 %s5; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,CIPLUS,NOTGFX9 %s6; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,CIPLUS,NOTGFX9 %s7; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,CIPLUS,GFX9 %s8; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,CIPLUS,GFX9 %s9 10; GCN-LABEL: {{^}}ds_append_lds:11; GCN: s_load_dword [[PTR:s[0-9]+]]12; GCN: s_mov_b32 m0, [[PTR]]13; GCN: ds_append [[RESULT:v[0-9]+]]{{$}}14; GCN-NOT: buffer_wbinvl115; GCN: {{.*}}store{{.*}} [[RESULT]]16define amdgpu_kernel void @ds_append_lds(ptr addrspace(3) %lds, ptr addrspace(1) %out) #0 {17 %val = call i32 @llvm.amdgcn.ds.append.p3(ptr addrspace(3) %lds, i1 false)18 store i32 %val, ptr addrspace(1) %out19 ret void20}21 22; GCN-LABEL: {{^}}ds_append_lds_max_offset:23; GCN: s_load_dword [[PTR:s[0-9]+]]24; GCN: s_mov_b32 m0, [[PTR]]25; GCN: ds_append [[RESULT:v[0-9]+]] offset:65532{{$}}26; GCN-NOT: buffer_wbinvl127; GCN: {{.*}}store{{.*}} [[RESULT]]28define amdgpu_kernel void @ds_append_lds_max_offset(ptr addrspace(3) %lds, ptr addrspace(1) %out) #0 {29 %gep = getelementptr inbounds i32, ptr addrspace(3) %lds, i32 1638330 %val = call i32 @llvm.amdgcn.ds.append.p3(ptr addrspace(3) %gep, i1 false)31 store i32 %val, ptr addrspace(1) %out32 ret void33}34 35; GCN-LABEL: {{^}}ds_append_no_fold_offset_si:36; GCN: s_load_dword [[PTR:s[0-9]+]]37 38; SI: s_add_i32 m0, [[PTR]], 1639; SI: ds_append [[RESULT:v[0-9]+]]{{$}}40 41; CIPLUS: s_mov_b32 m0, [[PTR]]42; CIPLUS: ds_append [[RESULT:v[0-9]+]] offset:16{{$}}43 44; GCN-NOT: buffer_wbinvl145; GCN: {{.*}}store{{.*}} [[RESULT]]46define amdgpu_kernel void @ds_append_no_fold_offset_si(ptr addrspace(4) %lds.ptr, ptr addrspace(1) %out) #0 {47 %lds = load ptr addrspace(3), ptr addrspace(4) %lds.ptr, align 448 %gep = getelementptr inbounds i32, ptr addrspace(3) %lds, i32 449 %val = call i32 @llvm.amdgcn.ds.append.p3(ptr addrspace(3) %gep, i1 false)50 store i32 %val, ptr addrspace(1) %out51 ret void52}53 54; GCN-LABEL: {{^}}ds_append_lds_over_max_offset:55; GCN: s_load_dword [[PTR:s[0-9]+]]56 57; SI: s_or_b32 m0, [[PTR]], 0x1000058; CIPLUSi|u: s_add_{{i|u}}32 m0, [[PTR]], 0x1000059 60; GCN: ds_append [[RESULT:v[0-9]+]]{{$}}61; GCN-NOT: buffer_wbinvl162; GCN: {{.*}}store{{.*}} [[RESULT]]63define amdgpu_kernel void @ds_append_lds_over_max_offset(ptr addrspace(3) %lds, ptr addrspace(1) %out) #0 {64 %gep = getelementptr inbounds i32, ptr addrspace(3) %lds, i32 1638465 %val = call i32 @llvm.amdgcn.ds.append.p3(ptr addrspace(3) %gep, i1 false)66 store i32 %val, ptr addrspace(1) %out67 ret void68}69 70; GCN-LABEL: {{^}}ds_append_lds_vgpr_addr:71; GCN: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v072; GCN: s_mov_b32 m0, [[READLANE]]73 74; GCN: ds_append [[RESULT:v[0-9]+]]{{$}}75; GCN-NOT: buffer_wbinvl176; GCN: {{.*}}store{{.*}} [[RESULT]]77define void @ds_append_lds_vgpr_addr(ptr addrspace(3) %lds, ptr addrspace(1) %out) #0 {78 %val = call i32 @llvm.amdgcn.ds.append.p3(ptr addrspace(3) %lds, i1 false)79 store i32 %val, ptr addrspace(1) %out80 ret void81}82 83; GCN-LABEL: {{^}}ds_append_gds:84; GCN: s_load_dword [[PTR:s[0-9]+]]85; GCN: s_mov_b32 m0, [[PTR]]86; GCN: ds_append [[RESULT:v[0-9]+]] gds{{$}}87; GCN-NOT: buffer_wbinvl188; GCN: {{.*}}store{{.*}} [[RESULT]]89define amdgpu_kernel void @ds_append_gds(ptr addrspace(2) %gds, ptr addrspace(1) %out) #0 {90 %val = call i32 @llvm.amdgcn.ds.append.p2(ptr addrspace(2) %gds, i1 false)91 store i32 %val, ptr addrspace(1) %out92 ret void93}94 95; GCN-LABEL: {{^}}ds_append_gds_max_offset:96; GCN: s_load_dword [[PTR:s[0-9]+]]97; GCN: s_mov_b32 m0, [[PTR]]98; GCN: ds_append [[RESULT:v[0-9]+]] offset:65532 gds{{$}}99; GCN-NOT: buffer_wbinvl1100; GCN: {{.*}}store{{.*}} [[RESULT]]101define amdgpu_kernel void @ds_append_gds_max_offset(ptr addrspace(2) %gds, ptr addrspace(1) %out) #0 {102 %gep = getelementptr inbounds i32, ptr addrspace(2) %gds, i32 16383103 %val = call i32 @llvm.amdgcn.ds.append.p2(ptr addrspace(2) %gep, i1 false)104 store i32 %val, ptr addrspace(1) %out105 ret void106}107 108; GCN-LABEL: {{^}}ds_append_gds_over_max_offset:109; GCN-NOT: buffer_wbinvl1110define amdgpu_kernel void @ds_append_gds_over_max_offset(ptr addrspace(2) %gds, ptr addrspace(1) %out) #0 {111 %gep = getelementptr inbounds i32, ptr addrspace(2) %gds, i32 16384112 %val = call i32 @llvm.amdgcn.ds.append.p2(ptr addrspace(2) %gep, i1 false)113 store i32 %val, ptr addrspace(1) %out114 ret void115}116 117; GCN-LABEL: {{^}}ds_append_lds_m0_restore:118; GCN: s_load_dword [[PTR:s[0-9]+]]119; GCN: s_mov_b32 m0, [[PTR]]120; GCN: ds_append [[RESULT:v[0-9]+]]{{$}}121; GCN-NOT: buffer_wbinvl1122; NOTGFX9: s_mov_b32 m0, -1123; GFX9-NOT: m0124; GCN: _store_dword125; GCN: ds_read_b32126define amdgpu_kernel void @ds_append_lds_m0_restore(ptr addrspace(3) %lds, ptr addrspace(1) %out) #0 {127 %val0 = call i32 @llvm.amdgcn.ds.append.p3(ptr addrspace(3) %lds, i1 false)128 store i32 %val0, ptr addrspace(1) %out129 %val1 = load volatile i32, ptr addrspace(3) %lds130 ret void131}132 133; Make sure this selects successfully with no use. The result register needs to be constrained.134; GCN-LABEL: {{^}}ds_append_lds_no_use:135; GCN: s_load_dword [[PTR:s[0-9]+]]136; GCN: s_mov_b32 m0, [[PTR]]137; GCN: ds_append [[RESULT:v[0-9]+]] offset:65532{{$}}138define amdgpu_kernel void @ds_append_lds_no_use(ptr addrspace(3) %lds, ptr addrspace(1) %out) #0 {139 %gep = getelementptr inbounds i32, ptr addrspace(3) %lds, i32 16383140 %val = call i32 @llvm.amdgcn.ds.append.p3(ptr addrspace(3) %gep, i1 false)141 ret void142}143 144declare i32 @llvm.amdgcn.ds.append.p3(ptr addrspace(3) nocapture, i1 immarg) #1145declare i32 @llvm.amdgcn.ds.append.p2(ptr addrspace(2) nocapture, i1 immarg) #1146 147attributes #0 = { nounwind }148attributes #1 = { argmemonly convergent nounwind }149