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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -stop-after=postrapseudos -o - < %s | FileCheck -enable-var-scope -check-prefix=MIR %s3 4 5define amdgpu_kernel void @gws_barrier_offset0(i32 %val) #0 {6 ; MIR-LABEL: name: gws_barrier_offset07 ; MIR: bb.0 (%ir-block.0):8 ; MIR-NEXT: liveins: $sgpr8_sgpr99 ; MIR-NEXT: {{ $}}10 ; MIR-NEXT: renamable $sgpr4 = S_LOAD_DWORD_IMM killed renamable $sgpr8_sgpr9, 0, 0 :: (dereferenceable invariant load (s32) from %ir.val.kernarg.offset, align 16, addrspace 4)11 ; MIR-NEXT: $m0 = S_MOV_B32 012 ; MIR-NEXT: $vgpr0 = V_MOV_B32_e32 killed $sgpr4, implicit $exec, implicit $exec13 ; MIR-NEXT: BUNDLE implicit killed renamable $vgpr0, implicit $m0, implicit $exec :: (load (s32) from custom "GWSResource") {14 ; MIR-NEXT: DS_GWS_BARRIER renamable $vgpr0, 0, implicit $m0, implicit $exec :: (load (s32) from custom "GWSResource")15 ; MIR-NEXT: S_WAITCNT 016 ; MIR-NEXT: }17 ; MIR-NEXT: S_ENDPGM 018 call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 0)19 ret void20}21 22 23declare void @llvm.amdgcn.ds.gws.barrier(i32, i32) #124 25attributes #0 = { nounwind }26attributes #1 = { convergent inaccessiblememonly nounwind }27