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1; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,LOOP %s2; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,LOOP %s3; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii < %s | FileCheck -check-prefixes=GCN,LOOP %s4; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii < %s | FileCheck -check-prefixes=GCN,LOOP %s5; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,LOOP %s6; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,LOOP %s7; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,NOLOOP %s8; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,NOLOOP %s9; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN,NOLOOP %s10; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN,NOLOOP %s11; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN,NOLOOP %s12; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN,NOLOOP %s13 14; Minimum offset15; GCN-LABEL: {{^}}gws_init_offset0:16; GCN-DAG: s_load_{{dword|b32}} [[BAR_NUM:s[0-9]+]]17; GCN-DAG: s_mov_b32 m0, 0{{$}}18; GCN: v_mov_b32_e32 v0, [[BAR_NUM]]19; NOLOOP: ds_gws_init v0 gds{{$}}20 21; LOOP: [[LOOP:.LBB[0-9]+_[0-9]+]]:22; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 023; LOOP-NEXT: ds_gws_init v0 gds24; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)25; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1)26; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 027; LOOP-NEXT: s_cbranch_scc1 [[LOOP]]28define amdgpu_kernel void @gws_init_offset0(i32 %val) #0 {29 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 0)30 ret void31}32 33; Maximum offset34; GCN-LABEL: {{^}}gws_init_offset63:35; NOLOOP-DAG: s_load_{{dword|b32}} [[BAR_NUM:s[0-9]+]]36; NOLOOP-DAG: s_mov_b32 m0, 0{{$}}37; NOLOOP-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]38; NOLOOP: ds_gws_init v0 offset:63 gds{{$}}39 40 41; LOOP: s_mov_b32 m0, 0{{$}}42; LOOP: [[LOOP:.LBB[0-9]+_[0-9]+]]:43; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 044; LOOP-NEXT: ds_gws_init v0 offset:63 gds45; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)46; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1)47; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 048; LOOP-NEXT: s_cbranch_scc1 [[LOOP]]49define amdgpu_kernel void @gws_init_offset63(i32 %val) #0 {50 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 63)51 ret void52}53 54; FIXME: Should be able to shift directly into m055; GCN-LABEL: {{^}}gws_init_sgpr_offset:56; NOLOOP-DAG: s_load_{{dwordx2|b64}} s[[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]]57 58; NOLOOP-DAG: s_lshl_b32 m0, s[[OFFSET]], 1659 60; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], s[[BAR_NUM]]61; NOLOOP: ds_gws_init [[GWS_VAL]] gds{{$}}62define amdgpu_kernel void @gws_init_sgpr_offset(i32 %val, i32 %offset) #0 {63 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %offset)64 ret void65}66 67; Variable offset in SGPR with constant add68; GCN-LABEL: {{^}}gws_init_sgpr_offset_add1:69; NOLOOP-DAG: s_load_{{dwordx2|b64}} s[[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]]70 71; NOLOOP-DAG: s_lshl_b32 m0, s[[OFFSET]], 1672 73; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], s[[BAR_NUM]]74; NOLOOP: ds_gws_init [[GWS_VAL]] offset:1 gds{{$}}75define amdgpu_kernel void @gws_init_sgpr_offset_add1(i32 %val, i32 %offset.base) #0 {76 %offset = add i32 %offset.base, 177 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %offset)78 ret void79}80 81; GCN-LABEL: {{^}}gws_init_vgpr_offset:82; NOLOOP-DAG: s_load_{{dword|b32}} [[BAR_NUM:s[0-9]+]]83; NOLOOP-DAG: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v084 85; NOLOOP-DAG: s_lshl_b32 m0, [[READLANE]], 1686 87; NOLOOP-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]88; NOLOOP: ds_gws_init v0 gds{{$}}89define amdgpu_kernel void @gws_init_vgpr_offset(i32 %val) #0 {90 %vgpr.offset = call i32 @llvm.amdgcn.workitem.id.x()91 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %vgpr.offset)92 ret void93}94 95; Variable offset in VGPR with constant add96; GCN-LABEL: {{^}}gws_init_vgpr_offset_add:97; NOLOOP-DAG: s_load_{{dword|b32}} [[BAR_NUM:s[0-9]+]]98; NOLOOP-DAG: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v099 100; NOLOOP-DAG: s_lshl_b32 m0, [[READLANE]], 16101 102; NOLOOP-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]103; NOLOOP: ds_gws_init v0 offset:3 gds{{$}}104define amdgpu_kernel void @gws_init_vgpr_offset_add(i32 %val) #0 {105 %vgpr.offset.base = call i32 @llvm.amdgcn.workitem.id.x()106 %vgpr.offset = add i32 %vgpr.offset.base, 3107 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %vgpr.offset)108 ret void109}110 111@lds = internal unnamed_addr addrspace(3) global i32 poison112 113; Check if m0 initialization is shared.114; GCN-LABEL: {{^}}gws_init_save_m0_init_constant_offset:115; NOLOOP: s_mov_b32 m0, 0116; NOLOOP: ds_gws_init v{{[0-9]+}} offset:10 gds117 118; LOOP: s_mov_b32 m0, -1119; LOOP: ds_write_b32120; LOOP: s_mov_b32 m0, 0121; LOOP: s_setreg_imm32_b32122; LOOP: ds_gws_init v{{[0-9]+}} offset:10 gds123; LOOP: s_cbranch_scc1124 125; LOOP: s_mov_b32 m0, -1126; LOOP: ds_write_b32127define amdgpu_kernel void @gws_init_save_m0_init_constant_offset(i32 %val) #0 {128 store volatile i32 1, ptr addrspace(3) @lds129 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 10)130 store i32 2, ptr addrspace(3) @lds131 ret void132}133 134; GCN-LABEL: {{^}}gws_init_lgkmcnt:135; NOLOOP: s_mov_b32 m0, 0{{$}}136; NOLOOP: ds_gws_init v0 gds{{$}}137; NOLOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)138; NOLOOP-NEXT: s_setpc_b64139define void @gws_init_lgkmcnt(i32 %val) {140 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 0)141 ret void142}143 144; Does not imply memory fence on its own145; GCN-LABEL: {{^}}gws_init_wait_before:146; NOLOOP: s_waitcnt lgkmcnt(0)147; NOLOOP-NOT: s_waitcnt148; NOLOOP: ds_gws_init149; NOLOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)150define amdgpu_kernel void @gws_init_wait_before(i32 %val, ptr addrspace(1) %ptr) #0 {151 store i32 0, ptr addrspace(1) %ptr152 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 7)153 ret void154}155 156declare void @llvm.amdgcn.ds.gws.init(i32, i32) #1157declare i32 @llvm.amdgcn.workitem.id.x() #2158 159attributes #0 = { nounwind }160attributes #1 = { convergent inaccessiblememonly nounwind writeonly }161attributes #2 = { nounwind readnone speculatable }162