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1; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefixes=GCN,FUNC %s2; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefixes=GCN,FUNC %s3; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s4; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s5; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s6; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s7 8; FUNC-LABEL: {{^}}ds_ordered_add:9; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 3110; GCN-DAG: s_mov_b32 m0,11; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds12define amdgpu_kernel void @ds_ordered_add(ptr addrspace(2) inreg %gds, ptr addrspace(1) %out) {13 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)14 store i32 %val, ptr addrspace(1) %out15 ret void16}17 18; Below are various modifications of input operands and shader types.19 20; FUNC-LABEL: {{^}}ds_ordered_add_counter2:21; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 3122; GCN-DAG: s_mov_b32 m0,23; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:776 gds24define amdgpu_kernel void @ds_ordered_add_counter2(ptr addrspace(2) inreg %gds, ptr addrspace(1) %out) {25 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 2, i1 true, i1 true)26 store i32 %val, ptr addrspace(1) %out27 ret void28}29 30; FUNC-LABEL: {{^}}ds_ordered_add_nodone:31; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 3132; GCN-DAG: s_mov_b32 m0,33; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:260 gds34define amdgpu_kernel void @ds_ordered_add_nodone(ptr addrspace(2) inreg %gds, ptr addrspace(1) %out) {35 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 false)36 store i32 %val, ptr addrspace(1) %out37 ret void38}39 40; FUNC-LABEL: {{^}}ds_ordered_add_norelease:41; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 3142; GCN-DAG: s_mov_b32 m0,43; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:4 gds44define amdgpu_kernel void @ds_ordered_add_norelease(ptr addrspace(2) inreg %gds, ptr addrspace(1) %out) {45 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 false, i1 false)46 store i32 %val, ptr addrspace(1) %out47 ret void48}49 50; FUNC-LABEL: {{^}}ds_ordered_add_cs:51; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 3152; GCN: s_mov_b32 m0, s053; VIGFX9-NEXT: s_nop 054; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds55; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)56define amdgpu_cs float @ds_ordered_add_cs(ptr addrspace(2) inreg %gds) {57 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)58 %r = bitcast i32 %val to float59 ret float %r60}61 62; FUNC-LABEL: {{^}}ds_ordered_add_default_cc:63; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 3164; GCN: s_mov_b32 m0, 0{{$}}65; VIGFX9-NEXT: s_nop 066; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds67; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)68define float @ds_ordered_add_default_cc() {69 %val = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) null, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)70 %r = bitcast i32 %val to float71 ret float %r72}73 74; FUNC-LABEL: {{^}}ds_ordered_add_fastcc:75; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 3176; GCN: s_mov_b32 m0, 0{{$}}77; VIGFX9-NEXT: s_nop 078; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds79; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)80define fastcc float @ds_ordered_add_fastcc() {81 %val = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) null, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)82 %r = bitcast i32 %val to float83 ret float %r84}85 86; FUNC-LABEL: {{^}}ds_ordered_add_func:87; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 3188; GCN: s_mov_b32 m0, 0{{$}}89; VIGFX9-NEXT: s_nop 090; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds91; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)92define float @ds_ordered_add_func() {93 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) null, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)94 %r = bitcast i32 %val to float95 ret float %r96}97 98; FUNC-LABEL: {{^}}ds_ordered_add_ps:99; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31100; GCN: s_mov_b32 m0, s0101; VIGFX9-NEXT: s_nop 0102; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:1796 gds103; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)104define amdgpu_ps float @ds_ordered_add_ps(ptr addrspace(2) inreg %gds) {105 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)106 %r = bitcast i32 %val to float107 ret float %r108}109 110; FUNC-LABEL: {{^}}ds_ordered_add_vs:111; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31112; GCN: s_mov_b32 m0, s0113; VIGFX9-NEXT: s_nop 0114; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:2820 gds115; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)116define amdgpu_vs float @ds_ordered_add_vs(ptr addrspace(2) inreg %gds) {117 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)118 %r = bitcast i32 %val to float119 ret float %r120}121 122; FUNC-LABEL: {{^}}ds_ordered_add_gs:123; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31124; GCN: s_mov_b32 m0, s0125; VIGFX9-NEXT: s_nop 0126; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:3844 gds127; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)128define amdgpu_gs float @ds_ordered_add_gs(ptr addrspace(2) inreg %gds) {129 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)130 %r = bitcast i32 %val to float131 ret float %r132}133 134declare i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) nocapture, i32, i32, i32, i1, i32, i1, i1)135