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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX950-SDAG %s3; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX950-GISEL %s4 5declare <2 x i32> @llvm.amdgcn.ds.read.tr4.b64.v2i32.p3(ptr addrspace(3))6declare <2 x i32> @llvm.amdgcn.ds.read.tr8.b64.v2i32.p3(ptr addrspace(3))7declare <3 x i32> @llvm.amdgcn.ds.read.tr6.b64.v3i32.p3(ptr addrspace(3))8declare <4 x i16> @llvm.amdgcn.ds.read.tr16.b64.v4i16.p3(ptr addrspace(3))9declare <4 x half> @llvm.amdgcn.ds.read.tr16.b64.v4f16.p3(ptr addrspace(3))10declare <4 x bfloat> @llvm.amdgcn.ds.read.tr16.b64.v4bf16.p3(ptr addrspace(3))11 12define amdgpu_ps void @ds_read_b64_tr_b4(ptr addrspace(3) %addr, ptr addrspace(1) %use) {13; GFX950-SDAG-LABEL: ds_read_b64_tr_b4:14; GFX950-SDAG: ; %bb.0: ; %entry15; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v216; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v117; GFX950-SDAG-NEXT: ds_read_b64_tr_b4 v[0:1], v0 offset:3218; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)19; GFX950-SDAG-NEXT: global_store_dwordx2 v[2:3], v[0:1], off20; GFX950-SDAG-NEXT: s_endpgm21;22; GFX950-GISEL-LABEL: ds_read_b64_tr_b4:23; GFX950-GISEL: ; %bb.0: ; %entry24; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v125; GFX950-GISEL-NEXT: ds_read_b64_tr_b4 v[0:1], v0 offset:3226; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v227; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)28; GFX950-GISEL-NEXT: global_store_dwordx2 v[4:5], v[0:1], off29; GFX950-GISEL-NEXT: s_endpgm30entry:31 %gep = getelementptr i64, ptr addrspace(3) %addr, i32 432 %val = call <2 x i32> @llvm.amdgcn.ds.read.tr4.b64.v2i32.p3(ptr addrspace(3) %gep)33 store <2 x i32> %val, ptr addrspace(1) %use34 ret void35}36 37define amdgpu_ps void @ds_read_b96_tr_b6(ptr addrspace(3) %addr, ptr addrspace(1) %use) {38; GFX950-SDAG-LABEL: ds_read_b96_tr_b6:39; GFX950-SDAG: ; %bb.0: ; %entry40; GFX950-SDAG-NEXT: ds_read_b96_tr_b6 v[4:6], v0 offset:3241; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v242; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v143; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)44; GFX950-SDAG-NEXT: global_store_dwordx3 v[2:3], v[4:6], off45; GFX950-SDAG-NEXT: s_endpgm46;47; GFX950-GISEL-LABEL: ds_read_b96_tr_b6:48; GFX950-GISEL: ; %bb.0: ; %entry49; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v150; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v251; GFX950-GISEL-NEXT: ds_read_b96_tr_b6 v[0:2], v0 offset:3252; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)53; GFX950-GISEL-NEXT: global_store_dwordx3 v[4:5], v[0:2], off54; GFX950-GISEL-NEXT: s_endpgm55entry:56 %gep = getelementptr i64, ptr addrspace(3) %addr, i32 457 %val = call <3 x i32> @llvm.amdgcn.ds.read.tr6.b96.v3i32.p3(ptr addrspace(3) %gep)58 store <3 x i32> %val, ptr addrspace(1) %use59 ret void60}61 62define amdgpu_ps void @ds_read_b64_tr_b8(ptr addrspace(3) %addr, ptr addrspace(1) %use) {63; GFX950-SDAG-LABEL: ds_read_b64_tr_b8:64; GFX950-SDAG: ; %bb.0: ; %entry65; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v266; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v167; GFX950-SDAG-NEXT: ds_read_b64_tr_b8 v[0:1], v0 offset:3268; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)69; GFX950-SDAG-NEXT: global_store_dwordx2 v[2:3], v[0:1], off70; GFX950-SDAG-NEXT: s_endpgm71;72; GFX950-GISEL-LABEL: ds_read_b64_tr_b8:73; GFX950-GISEL: ; %bb.0: ; %entry74; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v175; GFX950-GISEL-NEXT: ds_read_b64_tr_b8 v[0:1], v0 offset:3276; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v277; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)78; GFX950-GISEL-NEXT: global_store_dwordx2 v[4:5], v[0:1], off79; GFX950-GISEL-NEXT: s_endpgm80entry:81 %gep = getelementptr i64, ptr addrspace(3) %addr, i32 482 %val = call <2 x i32> @llvm.amdgcn.ds.read.tr8.b64.v2i32.p3(ptr addrspace(3) %gep)83 store <2 x i32> %val, ptr addrspace(1) %use84 ret void85}86 87define amdgpu_ps void @ds_read_b64_tr_b16(ptr addrspace(3) %addr, ptr addrspace(1) %use) {88; GFX950-SDAG-LABEL: ds_read_b64_tr_b16:89; GFX950-SDAG: ; %bb.0: ; %entry90; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v291; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v192; GFX950-SDAG-NEXT: ds_read_b64_tr_b16 v[0:1], v0 offset:3293; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)94; GFX950-SDAG-NEXT: global_store_dwordx2 v[2:3], v[0:1], off95; GFX950-SDAG-NEXT: s_endpgm96;97; GFX950-GISEL-LABEL: ds_read_b64_tr_b16:98; GFX950-GISEL: ; %bb.0: ; %entry99; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1100; GFX950-GISEL-NEXT: ds_read_b64_tr_b16 v[0:1], v0 offset:32101; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2102; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)103; GFX950-GISEL-NEXT: global_store_dwordx2 v[4:5], v[0:1], off104; GFX950-GISEL-NEXT: s_endpgm105entry:106 %gep = getelementptr i64, ptr addrspace(3) %addr, i32 4107 %val = call <4 x i16> @llvm.amdgcn.ds.read.tr16.b64.v4i16.p3(ptr addrspace(3) %gep)108 store <4 x i16> %val, ptr addrspace(1) %use109 ret void110}111 112define amdgpu_ps void @ds_read_b64_tr_b16_v4f16(ptr addrspace(3) %addr, ptr addrspace(1) %use) {113; GFX950-SDAG-LABEL: ds_read_b64_tr_b16_v4f16:114; GFX950-SDAG: ; %bb.0: ; %entry115; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2116; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1117; GFX950-SDAG-NEXT: ds_read_b64_tr_b16 v[0:1], v0 offset:32118; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)119; GFX950-SDAG-NEXT: global_store_dwordx2 v[2:3], v[0:1], off120; GFX950-SDAG-NEXT: s_endpgm121;122; GFX950-GISEL-LABEL: ds_read_b64_tr_b16_v4f16:123; GFX950-GISEL: ; %bb.0: ; %entry124; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1125; GFX950-GISEL-NEXT: ds_read_b64_tr_b16 v[0:1], v0 offset:32126; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2127; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)128; GFX950-GISEL-NEXT: global_store_dwordx2 v[4:5], v[0:1], off129; GFX950-GISEL-NEXT: s_endpgm130entry:131 %gep = getelementptr i64, ptr addrspace(3) %addr, i32 4132 %val = call <4 x half> @llvm.amdgcn.ds.read.tr16.b64.v4f16.p3(ptr addrspace(3) %gep)133 store <4 x half> %val, ptr addrspace(1) %use134 ret void135}136 137define amdgpu_ps void @ds_read_b64_tr_b16_v4bf16(ptr addrspace(3) %addr, ptr addrspace(1) %use) {138; GFX950-SDAG-LABEL: ds_read_b64_tr_b16_v4bf16:139; GFX950-SDAG: ; %bb.0: ; %entry140; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2141; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1142; GFX950-SDAG-NEXT: ds_read_b64_tr_b16 v[0:1], v0 offset:32143; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)144; GFX950-SDAG-NEXT: global_store_dwordx2 v[2:3], v[0:1], off145; GFX950-SDAG-NEXT: s_endpgm146;147; GFX950-GISEL-LABEL: ds_read_b64_tr_b16_v4bf16:148; GFX950-GISEL: ; %bb.0: ; %entry149; GFX950-GISEL-NEXT: v_mov_b32_e32 v3, v2150; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, v1151; GFX950-GISEL-NEXT: ds_read_b64_tr_b16 v[0:1], v0 offset:32152; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)153; GFX950-GISEL-NEXT: global_store_dwordx2 v[2:3], v[0:1], off154; GFX950-GISEL-NEXT: s_endpgm155entry:156 %gep = getelementptr i64, ptr addrspace(3) %addr, i32 4157 %val = call <4 x bfloat> @llvm.amdgcn.ds.read.tr16.b64.v4bf16.p3(ptr addrspace(3) %gep)158 store <4 x bfloat> %val, ptr addrspace(1) %use159 ret void160}161 162; This is a special case that does not require aligned VGPRs. Make163; sure no copies are required for the unaligned ABI return value.164define { i32, <3 x i32> } @ds_read_b96_tr_b6_no_align2_requirement(ptr addrspace(3) %ptr) {165; GFX950-SDAG-LABEL: ds_read_b96_tr_b6_no_align2_requirement:166; GFX950-SDAG: ; %bb.0:167; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)168; GFX950-SDAG-NEXT: ds_read_b96_tr_b6 v[2:4], v0 offset:32169; GFX950-SDAG-NEXT: v_mov_b32_e32 v0, 0170; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)171; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, v2172; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v3173; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v4174; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]175;176; GFX950-GISEL-LABEL: ds_read_b96_tr_b6_no_align2_requirement:177; GFX950-GISEL: ; %bb.0:178; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)179; GFX950-GISEL-NEXT: ds_read_b96_tr_b6 v[2:4], v0 offset:32180; GFX950-GISEL-NEXT: v_mov_b32_e32 v0, 0181; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)182; GFX950-GISEL-NEXT: v_mov_b32_e32 v1, v2183; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, v3184; GFX950-GISEL-NEXT: v_mov_b32_e32 v3, v4185; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]186 %gep = getelementptr i64, ptr addrspace(3) %ptr, i32 4187 %val = call <3 x i32> @llvm.amdgcn.ds.read.tr6.b96.v3i32.p3(ptr addrspace(3) %gep)188 %insert0 = insertvalue { i32, <3 x i32> } poison, i32 0, 0189 %insert1 = insertvalue { i32, <3 x i32> } %insert0, <3 x i32> %val, 1190 ret { i32, <3 x i32> } %insert1191}192 193define void @ds_read_b96_tr_b6_no_align2_requirement_agpr(ptr addrspace(3) %ptr) {194; GFX950-SDAG-LABEL: ds_read_b96_tr_b6_no_align2_requirement_agpr:195; GFX950-SDAG: ; %bb.0:196; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)197; GFX950-SDAG-NEXT: ds_read_b96_tr_b6 v[0:2], v0 offset:32198; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)199; GFX950-SDAG-NEXT: v_accvgpr_write_b32 a1, v0200; GFX950-SDAG-NEXT: v_accvgpr_write_b32 a2, v1201; GFX950-SDAG-NEXT: v_accvgpr_write_b32 a3, v2202; GFX950-SDAG-NEXT: ;;#ASMSTART203; GFX950-SDAG-NEXT: ; use a1 a2 a3204; GFX950-SDAG-NEXT: ;;#ASMEND205; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]206;207; GFX950-GISEL-LABEL: ds_read_b96_tr_b6_no_align2_requirement_agpr:208; GFX950-GISEL: ; %bb.0:209; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)210; GFX950-GISEL-NEXT: ds_read_b96_tr_b6 v[0:2], v0 offset:32211; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)212; GFX950-GISEL-NEXT: v_accvgpr_write_b32 a1, v0213; GFX950-GISEL-NEXT: v_accvgpr_write_b32 a2, v1214; GFX950-GISEL-NEXT: v_accvgpr_write_b32 a3, v2215; GFX950-GISEL-NEXT: ;;#ASMSTART216; GFX950-GISEL-NEXT: ; use a1 a2 a3217; GFX950-GISEL-NEXT: ;;#ASMEND218; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]219 %gep = getelementptr i64, ptr addrspace(3) %ptr, i32 4220 %val = call <3 x i32> @llvm.amdgcn.ds.read.tr6.b96.v3i32.p3(ptr addrspace(3) %gep)221 %val0 = extractelement <3 x i32> %val, i32 0222 %val1 = extractelement <3 x i32> %val, i32 1223 %val2 = extractelement <3 x i32> %val, i32 2224 call void asm sideeffect "; use $0 $1 $2", "{a1},{a2},{a3}"(i32 %val0, i32 %val1, i32 %val2)225 ret void226}227