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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s3; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s4 5declare i32 @llvm.amdgcn.ds.sub.gs.reg.rtn.i32(i32, i32 immarg)6declare i64 @llvm.amdgcn.ds.sub.gs.reg.rtn.i64(i32, i32 immarg)7 8define amdgpu_gs void @test_sub_32(i32 %arg) {9; CHECK-LABEL: test_sub_32:10; CHECK: ; %bb.0:11; CHECK-NEXT: ds_sub_gs_reg_rtn v[0:1], v0 offset:16 gds12; CHECK-NEXT: s_waitcnt lgkmcnt(0)13; CHECK-NEXT: s_nop 014; CHECK-NEXT: s_endpgm15 %unused = call i32 @llvm.amdgcn.ds.sub.gs.reg.rtn.i32(i32 %arg, i32 16)16 ret void17}18 19define amdgpu_gs void @test_sub_32_use(i32 %arg, ptr addrspace(1) %out) {20; CHECK-LABEL: test_sub_32_use:21; CHECK: ; %bb.0:22; CHECK-NEXT: ds_sub_gs_reg_rtn v[3:4], v0 offset:16 gds23; CHECK-NEXT: s_waitcnt lgkmcnt(0)24; CHECK-NEXT: global_store_b32 v[1:2], v3, off25; CHECK-NEXT: s_endpgm26 %res = call i32 @llvm.amdgcn.ds.sub.gs.reg.rtn.i32(i32 %arg, i32 16)27 store i32 %res, ptr addrspace(1) %out, align 428 ret void29}30 31define amdgpu_gs void @test_sub_64(i32 %arg) {32; CHECK-LABEL: test_sub_64:33; CHECK: ; %bb.0:34; CHECK-NEXT: ds_sub_gs_reg_rtn v[0:1], v0 offset:32 gds35; CHECK-NEXT: s_waitcnt lgkmcnt(0)36; CHECK-NEXT: s_nop 037; CHECK-NEXT: s_endpgm38 %unused = call i64 @llvm.amdgcn.ds.sub.gs.reg.rtn.i64(i32 %arg, i32 32)39 ret void40}41 42define amdgpu_gs void @test_sub_64_use(i32 %arg, ptr addrspace(1) %out) {43; CHECK-LABEL: test_sub_64_use:44; CHECK: ; %bb.0:45; CHECK-NEXT: ds_sub_gs_reg_rtn v[3:4], v0 offset:32 gds46; CHECK-NEXT: s_waitcnt lgkmcnt(0)47; CHECK-NEXT: global_store_b64 v[1:2], v[3:4], off48; CHECK-NEXT: s_endpgm49 %res = call i64 @llvm.amdgcn.ds.sub.gs.reg.rtn.i64(i32 %arg, i32 32)50 store i64 %res, ptr addrspace(1) %out, align 451 ret void52}53 54