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1; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -strict-whitespace -check-prefixes=GCN,GFX8,PREGFX11 %s2; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -strict-whitespace -check-prefixes=GCN,GFX10,PREGFX11 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -strict-whitespace -check-prefixes=GCN,GFX11 %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-vopd=0 < %s | FileCheck -strict-whitespace -check-prefixes=GCN,GFX11 %s5 6declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #17declare void @llvm.amdgcn.exp.i32(i32, i32, i32, i32, i32, i32, i1, i1) #18declare float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8), i32, i32, i32) #29 10; GCN-LABEL: {{^}}test_export_zeroes_f32:11; GCN: {{exp|export}} mrt0 off, off, off, off{{$}}12; GCN: {{exp|export}} mrt0 off, off, off, off done{{$}}13define amdgpu_kernel void @test_export_zeroes_f32() #0 {14 15 call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float 0.0, float 0.0, float 0.0, float 0.0, i1 false, i1 false)16 call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float 0.0, float 0.0, float 0.0, float 0.0, i1 true, i1 false)17 ret void18}19 20; FIXME: Should not set up registers for the unused source registers.21 22; GCN-LABEL: {{^}}test_export_en_src0_f32:23; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.024; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.025; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.526; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.027; GCN: {{exp|export}} mrt0 [[SRC0]], off, off, off done{{$}}28define amdgpu_kernel void @test_export_en_src0_f32() #0 {29 call void @llvm.amdgcn.exp.f32(i32 0, i32 1, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)30 ret void31}32 33; GCN-LABEL: {{^}}test_export_en_src1_f32:34; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.035; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.036; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.537; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.038; GCN: {{exp|export}} mrt0 off, [[SRC1]], off, off done{{$}}39define amdgpu_kernel void @test_export_en_src1_f32() #0 {40 call void @llvm.amdgcn.exp.f32(i32 0, i32 2, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)41 ret void42}43 44; GCN-LABEL: {{^}}test_export_en_src2_f32:45; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.046; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.047; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.548; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.049; GCN: {{exp|export}} mrt0 off, off, [[SRC2]], off done{{$}}50define amdgpu_kernel void @test_export_en_src2_f32() #0 {51 call void @llvm.amdgcn.exp.f32(i32 0, i32 4, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)52 ret void53}54 55; GCN-LABEL: {{^}}test_export_en_src3_f32:56; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.057; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.058; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.559; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.060; GCN: {{exp|export}} mrt0 off, off, off, [[SRC3]] done{{$}}61define amdgpu_kernel void @test_export_en_src3_f32() #0 {62 call void @llvm.amdgcn.exp.f32(i32 0, i32 8, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)63 ret void64}65 66; GCN-LABEL: {{^}}test_export_en_src0_src1_f32:67; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.068; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.069; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.570; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.071; GCN: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], off, off done{{$}}72define amdgpu_kernel void @test_export_en_src0_src1_f32() #0 {73 call void @llvm.amdgcn.exp.f32(i32 0, i32 3, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)74 ret void75}76 77; GCN-LABEL: {{^}}test_export_en_src0_src2_f32:78; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.079; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.080; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.581; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.082; GCN: {{exp|export}} mrt0 [[SRC0]], off, [[SRC2]], off done{{$}}83define amdgpu_kernel void @test_export_en_src0_src2_f32() #0 {84 call void @llvm.amdgcn.exp.f32(i32 0, i32 5, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)85 ret void86}87 88; GCN-LABEL: {{^}}test_export_en_src0_src3_f32:89; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.090; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.091; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.592; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.093; GCN: {{exp|export}} mrt0 [[SRC0]], off, off, [[SRC3]]{{$}}94; GCN: {{exp|export}} mrt0 [[SRC0]], off, off, [[SRC3]] done{{$}}95define amdgpu_kernel void @test_export_en_src0_src3_f32() #0 {96 call void @llvm.amdgcn.exp.f32(i32 0, i32 9, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false)97 call void @llvm.amdgcn.exp.f32(i32 0, i32 9, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)98 ret void99}100 101; GCN-LABEL: {{^}}test_export_en_src0_src1_src2_src3_f32:102; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0103; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0104; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5105; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0106; GCN: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}107; GCN: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}108define amdgpu_kernel void @test_export_en_src0_src1_src2_src3_f32() #0 {109 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false)110 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)111 ret void112}113 114; GCN-LABEL: {{^}}test_export_mrt7_f32:115; GCN-DAG: v_mov_b32_e32 [[VHALF:v[0-9]+]], 0.5116; GCN: {{exp|export}} mrt7 [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]]{{$}}117; GCN: {{exp|export}} mrt7 [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]] done{{$}}118define amdgpu_kernel void @test_export_mrt7_f32() #0 {119 call void @llvm.amdgcn.exp.f32(i32 7, i32 15, float 0.5, float 0.5, float 0.5, float 0.5, i1 false, i1 false)120 call void @llvm.amdgcn.exp.f32(i32 7, i32 15, float 0.5, float 0.5, float 0.5, float 0.5, i1 true, i1 false)121 ret void122}123 124; GCN-LABEL: {{^}}test_export_z_f32:125; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0126; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0127; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5128; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0129; GCN: {{exp|export}} mrtz [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}130; GCN: {{exp|export}} mrtz [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}131define amdgpu_kernel void @test_export_z_f32() #0 {132 call void @llvm.amdgcn.exp.f32(i32 8, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false)133 call void @llvm.amdgcn.exp.f32(i32 8, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)134 ret void135}136 137; GCN-LABEL: {{^}}test_export_null_f32:138; PREGFX11-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0139; PREGFX11-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0140; PREGFX11-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5141; PREGFX11-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0142; PREGFX11: {{exp|export}} null [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}143; PREGFX11: {{exp|export}} null [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}144define amdgpu_kernel void @test_export_null_f32() #0 {145 call void @llvm.amdgcn.exp.f32(i32 9, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false)146 call void @llvm.amdgcn.exp.f32(i32 9, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)147 ret void148}149 150; GCN-LABEL: {{^}}test_export_reserved10_f32:151; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0152; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0153; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5154; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0155; GCN: {{exp|export}} invalid_target_10 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}156; GCN: {{exp|export}} invalid_target_10 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}157define amdgpu_kernel void @test_export_reserved10_f32() #0 {158 call void @llvm.amdgcn.exp.f32(i32 10, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false)159 call void @llvm.amdgcn.exp.f32(i32 10, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)160 ret void161}162 163; GCN-LABEL: {{^}}test_export_reserved11_f32:164; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0165; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0166; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5167; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0168; GCN: {{exp|export}} invalid_target_11 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}169; GCN: {{exp|export}} invalid_target_11 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}170define amdgpu_kernel void @test_export_reserved11_f32() #0 {171 call void @llvm.amdgcn.exp.f32(i32 11, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false)172 call void @llvm.amdgcn.exp.f32(i32 11, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)173 ret void174}175 176; GCN-LABEL: {{^}}test_export_pos0_f32:177; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0178; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0179; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5180; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0181; GCN: {{exp|export}} pos0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}182; GCN: {{exp|export}} pos0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}183define amdgpu_kernel void @test_export_pos0_f32() #0 {184 call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false)185 call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)186 ret void187}188 189; GCN-LABEL: {{^}}test_export_pos3_f32:190; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0191; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0192; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5193; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0194; GCN: {{exp|export}} pos3 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}195; GCN: {{exp|export}} pos3 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}196define amdgpu_kernel void @test_export_pos3_f32() #0 {197 call void @llvm.amdgcn.exp.f32(i32 15, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false)198 call void @llvm.amdgcn.exp.f32(i32 15, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)199 ret void200}201 202; GCN-LABEL: {{^}}test_export_param0_f32:203; PREGFX11-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0204; PREGFX11-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0205; PREGFX11-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5206; PREGFX11-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0207; PREGFX11: {{exp|export}} param0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}208; PREGFX11: {{exp|export}} param0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}209define amdgpu_kernel void @test_export_param0_f32() #0 {210 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false)211 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)212 ret void213}214 215; GCN-LABEL: {{^}}test_export_param31_f32:216; PREGFX11-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0217; PREGFX11-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0218; PREGFX11-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5219; PREGFX11-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0220; PREGFX11: {{exp|export}} param31 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}221; PREGFX11: {{exp|export}} param31 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}222define amdgpu_kernel void @test_export_param31_f32() #0 {223 call void @llvm.amdgcn.exp.f32(i32 63, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false)224 call void @llvm.amdgcn.exp.f32(i32 63, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)225 ret void226}227 228; GCN-LABEL: {{^}}test_export_vm_f32:229; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0230; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0231; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5232; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0233; PREGFX11: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] vm{{$}}234; PREGFX11: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done vm{{$}}235; GFX11: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}236; GFX11: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}237define amdgpu_kernel void @test_export_vm_f32() #0 {238 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 true)239 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 true)240 ret void241}242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257; GCN-LABEL: {{^}}test_export_zeroes_i32:258; GCN: {{exp|export}} mrt0 off, off, off, off{{$}}259; GCN: {{exp|export}} mrt0 off, off, off, off done{{$}}260define amdgpu_kernel void @test_export_zeroes_i32() #0 {261 262 call void @llvm.amdgcn.exp.i32(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i1 false, i1 false)263 call void @llvm.amdgcn.exp.i32(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i1 true, i1 false)264 ret void265}266 267; FIXME: Should not set up registers for the unused source registers.268 269; GCN-LABEL: {{^}}test_export_en_src0_i32:270; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1271; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2272; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5273; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4274; GCN: {{exp|export}} mrt0 [[SRC0]], off, off, off done{{$}}275define amdgpu_kernel void @test_export_en_src0_i32() #0 {276 call void @llvm.amdgcn.exp.i32(i32 0, i32 1, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false)277 ret void278}279 280; GCN-LABEL: {{^}}test_export_en_src1_i32:281; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1282; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2283; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5284; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4285; GCN: {{exp|export}} mrt0 off, [[SRC1]], off, off done{{$}}286define amdgpu_kernel void @test_export_en_src1_i32() #0 {287 call void @llvm.amdgcn.exp.i32(i32 0, i32 2, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false)288 ret void289}290 291; GCN-LABEL: {{^}}test_export_en_src2_i32:292; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1293; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2294; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5295; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4296; GCN: {{exp|export}} mrt0 off, off, [[SRC2]], off done{{$}}297define amdgpu_kernel void @test_export_en_src2_i32() #0 {298 call void @llvm.amdgcn.exp.i32(i32 0, i32 4, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false)299 ret void300}301 302; GCN-LABEL: {{^}}test_export_en_src3_i32:303; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1304; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2305; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5306; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4307; GCN: {{exp|export}} mrt0 off, off, off, [[SRC3]] done{{$}}308define amdgpu_kernel void @test_export_en_src3_i32() #0 {309 call void @llvm.amdgcn.exp.i32(i32 0, i32 8, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false)310 ret void311}312 313; GCN-LABEL: {{^}}test_export_en_src0_src1_i32:314; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1315; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2316; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5317; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4318; GCN: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], off, off done{{$}}319define amdgpu_kernel void @test_export_en_src0_src1_i32() #0 {320 call void @llvm.amdgcn.exp.i32(i32 0, i32 3, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false)321 ret void322}323 324; GCN-LABEL: {{^}}test_export_en_src0_src2_i32:325; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1326; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2327; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5328; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4329; GCN: {{exp|export}} mrt0 [[SRC0]], off, [[SRC2]], off done{{$}}330define amdgpu_kernel void @test_export_en_src0_src2_i32() #0 {331 call void @llvm.amdgcn.exp.i32(i32 0, i32 5, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false)332 ret void333}334 335; GCN-LABEL: {{^}}test_export_en_src0_src3_i32:336; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1337; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2338; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5339; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4340; GCN: {{exp|export}} mrt0 [[SRC0]], off, off, [[SRC3]]{{$}}341; GCN: {{exp|export}} mrt0 [[SRC0]], off, off, [[SRC3]] done{{$}}342define amdgpu_kernel void @test_export_en_src0_src3_i32() #0 {343 call void @llvm.amdgcn.exp.i32(i32 0, i32 9, i32 1, i32 2, i32 5, i32 4, i1 false, i1 false)344 call void @llvm.amdgcn.exp.i32(i32 0, i32 9, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false)345 ret void346}347 348; GCN-LABEL: {{^}}test_export_en_src0_src1_src2_src3_i32:349; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1350; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2351; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5352; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4353; GCN: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}354; GCN: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}355define amdgpu_kernel void @test_export_en_src0_src1_src2_src3_i32() #0 {356 call void @llvm.amdgcn.exp.i32(i32 0, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 false)357 call void @llvm.amdgcn.exp.i32(i32 0, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false)358 ret void359}360 361; GCN-LABEL: {{^}}test_export_mrt7_i32:362; GCN-DAG: v_mov_b32_e32 [[VHALF:v[0-9]+]], 5363; GCN: {{exp|export}} mrt7 [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]]{{$}}364; GCN: {{exp|export}} mrt7 [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]] done{{$}}365define amdgpu_kernel void @test_export_mrt7_i32() #0 {366 call void @llvm.amdgcn.exp.i32(i32 7, i32 15, i32 5, i32 5, i32 5, i32 5, i1 false, i1 false)367 call void @llvm.amdgcn.exp.i32(i32 7, i32 15, i32 5, i32 5, i32 5, i32 5, i1 true, i1 false)368 ret void369}370 371; GCN-LABEL: {{^}}test_export_z_i32:372; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1373; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2374; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5375; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4376; GCN: {{exp|export}} mrtz [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}377; GCN: {{exp|export}} mrtz [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}378define amdgpu_kernel void @test_export_z_i32() #0 {379 call void @llvm.amdgcn.exp.i32(i32 8, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 false)380 call void @llvm.amdgcn.exp.i32(i32 8, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false)381 ret void382}383 384; GCN-LABEL: {{^}}test_export_null_i32:385; PREGFX11-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1386; PREGFX11-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2387; PREGFX11-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5388; PREGFX11-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4389; PREGFX11: {{exp|export}} null [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}390; PREGFX11: {{exp|export}} null [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}391define amdgpu_kernel void @test_export_null_i32() #0 {392 call void @llvm.amdgcn.exp.i32(i32 9, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 false)393 call void @llvm.amdgcn.exp.i32(i32 9, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false)394 ret void395}396 397; GCN-LABEL: {{^}}test_export_reserved10_i32:398; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1399; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2400; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5401; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4402; GCN: {{exp|export}} invalid_target_10 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}403; GCN: {{exp|export}} invalid_target_10 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}404define amdgpu_kernel void @test_export_reserved10_i32() #0 {405 call void @llvm.amdgcn.exp.i32(i32 10, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 false)406 call void @llvm.amdgcn.exp.i32(i32 10, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false)407 ret void408}409 410; GCN-LABEL: {{^}}test_export_reserved11_i32:411; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1412; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2413; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5414; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4415; GCN: {{exp|export}} invalid_target_11 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}416; GCN: {{exp|export}} invalid_target_11 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}417define amdgpu_kernel void @test_export_reserved11_i32() #0 {418 call void @llvm.amdgcn.exp.i32(i32 11, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 false)419 call void @llvm.amdgcn.exp.i32(i32 11, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false)420 ret void421}422 423; GCN-LABEL: {{^}}test_export_pos0_i32:424; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1425; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2426; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5427; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4428; GCN: {{exp|export}} pos0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}429; GCN: {{exp|export}} pos0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}430define amdgpu_kernel void @test_export_pos0_i32() #0 {431 call void @llvm.amdgcn.exp.i32(i32 12, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 false)432 call void @llvm.amdgcn.exp.i32(i32 12, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false)433 ret void434}435 436; GCN-LABEL: {{^}}test_export_pos3_i32:437; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1438; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2439; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5440; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4441; GCN: {{exp|export}} pos3 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}442; GCN: {{exp|export}} pos3 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}443define amdgpu_kernel void @test_export_pos3_i32() #0 {444 call void @llvm.amdgcn.exp.i32(i32 15, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 false)445 call void @llvm.amdgcn.exp.i32(i32 15, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false)446 ret void447}448 449; GCN-LABEL: {{^}}test_export_param0_i32:450; PREGFX11-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1451; PREGFX11-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2452; PREGFX11-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5453; PREGFX11-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4454; PREGFX11: {{exp|export}} param0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}455; PREGFX11: {{exp|export}} param0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}456define amdgpu_kernel void @test_export_param0_i32() #0 {457 call void @llvm.amdgcn.exp.i32(i32 32, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 false)458 call void @llvm.amdgcn.exp.i32(i32 32, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false)459 ret void460}461 462; GCN-LABEL: {{^}}test_export_param31_i32:463; PREGFX11-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1464; PREGFX11-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2465; PREGFX11-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5466; PREGFX11-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4467; PREGFX11: {{exp|export}} param31 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}468; PREGFX11: {{exp|export}} param31 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}469define amdgpu_kernel void @test_export_param31_i32() #0 {470 call void @llvm.amdgcn.exp.i32(i32 63, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 false)471 call void @llvm.amdgcn.exp.i32(i32 63, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false)472 ret void473}474 475; GCN-LABEL: {{^}}test_export_vm_i32:476; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1477; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2478; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5479; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4480; PREGFX11: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] vm{{$}}481; PREGFX11: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done vm{{$}}482; GFX11: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}483; GFX11: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}484define amdgpu_kernel void @test_export_vm_i32() #0 {485 call void @llvm.amdgcn.exp.i32(i32 0, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 true)486 call void @llvm.amdgcn.exp.i32(i32 0, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 true)487 ret void488}489 490; GCN-LABEL: {{^}}test_if_export_f32:491; GCN: s_cbranch_execz492; GCN: exp493define amdgpu_ps void @test_if_export_f32(i32 %flag, float %x, float %y, float %z, float %w) #0 {494 %cc = icmp eq i32 %flag, 0495 br i1 %cc, label %end, label %exp496 497exp:498 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 false, i1 false)499 br label %end500 501end:502 ret void503}504 505; GCN-LABEL: {{^}}test_if_export_vm_f32:506; GCN: s_cbranch_execz507; GCN: exp508define amdgpu_ps void @test_if_export_vm_f32(i32 %flag, float %x, float %y, float %z, float %w) #0 {509 %cc = icmp eq i32 %flag, 0510 br i1 %cc, label %end, label %exp511 512exp:513 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 false, i1 true)514 br label %end515 516end:517 ret void518}519 520; GCN-LABEL: {{^}}test_if_export_done_f32:521; GCN: s_cbranch_execz522; GCN: exp523define amdgpu_ps void @test_if_export_done_f32(i32 %flag, float %x, float %y, float %z, float %w) #0 {524 %cc = icmp eq i32 %flag, 0525 br i1 %cc, label %end, label %exp526 527exp:528 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 true, i1 false)529 br label %end530 531end:532 ret void533}534 535; GCN-LABEL: {{^}}test_if_export_vm_done_f32:536; GCN: s_cbranch_execz537; GCN: exp538define amdgpu_ps void @test_if_export_vm_done_f32(i32 %flag, float %x, float %y, float %z, float %w) #0 {539 %cc = icmp eq i32 %flag, 0540 br i1 %cc, label %end, label %exp541 542exp:543 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 true, i1 true)544 br label %end545 546end:547 ret void548}549 550; GCN-LABEL: {{^}}test_export_clustering:551; PREGFX11-DAG: v_mov_b32_e32 [[W0:v[0-9]+]], 0552; PREGFX11-DAG: v_mov_b32_e32 [[W1:v[0-9]+]], 1.0553 554; GFX8-DAG: v_mov_b32_e32 [[X:v[0-9]+]], s1555; GFX8-DAG: v_mov_b32_e32 [[Y:v[0-9]+]], s0556; GFX8-DAG: v_add_f32_e{{32|64}} [[Z0:v[0-9]+]]557; GFX8-DAG: v_sub_f32_e{{32|64}} [[Z1:v[0-9]+]]558; GFX8: {{exp|export}} param0 [[Y]], [[X]], [[Z0]], [[W0]]{{$}}559; GFX8-NEXT: {{exp|export}} param1 [[Y]], [[X]], [[Z1]], [[W1]] done{{$}}560 561; GFX10-DAG: v_mov_b32_e32 [[X:v[0-9]+]], s0562; GFX10-DAG: v_mov_b32_e32 [[Y:v[0-9]+]], s1563; GFX10-DAG: v_add_f32_e{{32|64}} [[Z0:v[0-9]+]]564; GFX10-DAG: v_sub_f32_e{{32|64}} [[Z1:v[0-9]+]]565; GFX10: {{exp|export}} param0 [[X]], [[Y]], [[Z0]], [[W0]]{{$}}566; GFX10-NEXT: {{exp|export}} param1 [[X]], [[Y]], [[Z1]], [[W1]] done{{$}}567define amdgpu_kernel void @test_export_clustering(float %x, float %y) #0 {568 %z0 = fadd float %x, %y569 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %x, float %y, float %z0, float 0.0, i1 false, i1 false)570 %z1 = fsub float %y, %x571 call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float %x, float %y, float %z1, float 1.0, i1 true, i1 false)572 ret void573}574 575; GCN-LABEL: {{^}}test_export_pos_before_param:576; PREGFX11: {{exp|export}} pos0577; PREGFX11-NOT: s_waitcnt578; PREGFX11: {{exp|export}} param0579define amdgpu_kernel void @test_export_pos_before_param(float %x, float %y) #0 {580 %z0 = fadd float %x, %y581 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float 1.0, float 1.0, float 1.0, float %z0, i1 false, i1 false)582 %z1 = fsub float %y, %x583 call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float 0.0, float 0.0, float 0.0, float %z1, i1 true, i1 false)584 ret void585}586 587; GCN-LABEL: {{^}}test_export_pos4_before_param:588; GFX10: {{exp|export}} pos4589; GFX10-NOT: s_waitcnt590; GFX10: {{exp|export}} param0591define amdgpu_kernel void @test_export_pos4_before_param(float %x, float %y) #0 {592 %z0 = fadd float %x, %y593 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float 1.0, float 1.0, float 1.0, float %z0, i1 false, i1 false)594 %z1 = fsub float %y, %x595 call void @llvm.amdgcn.exp.f32(i32 16, i32 15, float 0.0, float 0.0, float 0.0, float %z1, i1 true, i1 false)596 ret void597}598 599; GCN-LABEL: {{^}}test_export_pos_before_param_ordered:600; PREGFX11: {{exp|export}} pos0601; PREGFX11: {{exp|export}} pos1602; PREGFX11: {{exp|export}} pos2603; PREGFX11-NOT: s_waitcnt604; PREGFX11: {{exp|export}} param0605; PREGFX11: {{exp|export}} param1606; PREGFX11: {{exp|export}} param2607define amdgpu_kernel void @test_export_pos_before_param_ordered(float %x, float %y) #0 {608 %z0 = fadd float %x, %y609 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float 1.0, float 1.0, float 1.0, float %z0, i1 false, i1 false)610 call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float 1.0, float 1.0, float 1.0, float %z0, i1 false, i1 false)611 call void @llvm.amdgcn.exp.f32(i32 34, i32 15, float 1.0, float 1.0, float 1.0, float %z0, i1 false, i1 false)612 %z1 = fsub float %y, %x613 call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float 0.0, float 0.0, float 0.0, float %z1, i1 false, i1 false)614 call void @llvm.amdgcn.exp.f32(i32 13, i32 15, float 0.0, float 0.0, float 0.0, float %z1, i1 false, i1 false)615 call void @llvm.amdgcn.exp.f32(i32 14, i32 15, float 0.0, float 0.0, float 0.0, float %z1, i1 true, i1 false)616 ret void617}618 619; GCN-LABEL: {{^}}test_export_pos_before_param_across_load:620; PREGFX11: {{exp|export}} pos0621; PREGFX11-NEXT: {{exp|export}} param0622; PREGFX11-NEXT: {{exp|export}} param1623define amdgpu_kernel void @test_export_pos_before_param_across_load(i32 %idx) #0 {624 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float 1.0, float 1.0, float 1.0, float 1.0, i1 false, i1 false)625 call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float 1.0, float 1.0, float 1.0, float 0.5, i1 false, i1 false)626 %load = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) poison, i32 %idx, i32 0, i32 0)627 call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float 0.0, float 0.0, float 0.0, float %load, i1 true, i1 false)628 ret void629}630 631; GCN-LABEL: {{^}}test_export_across_store_load:632; PREGFX11: buffer_store633; PREGFX11: buffer_load634; PREGFX11: {{exp|export}} pos0635; PREGFX11: {{exp|export}} param0636; PREGFX11: {{exp|export}} param1637define amdgpu_kernel void @test_export_across_store_load(i32 %idx, float %v) #0 {638 %data0 = alloca <4 x float>, align 8, addrspace(5)639 %data1 = alloca <4 x float>, align 8, addrspace(5)640 %cmp = icmp eq i32 %idx, 1641 %data = select i1 %cmp, ptr addrspace(5) %data0, ptr addrspace(5) %data1642 store float %v, ptr addrspace(5) %data, align 8643 call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float 0.0, float 0.0, float 0.0, float 1.0, i1 true, i1 false)644 %load0 = load float, ptr addrspace(5) %data0, align 8645 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %load0, float 0.0, float 1.0, float 0.0, i1 false, i1 false)646 call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float %load0, float 0.0, float 1.0, float 0.0, i1 false, i1 false)647 ret void648}649 650attributes #0 = { nounwind }651attributes #1 = { nounwind inaccessiblememonly }652attributes #2 = { nounwind readnone }653