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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefixes=GFX113; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefixes=GFX114; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s -check-prefixes=GFX125; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s -check-prefixes=GFX126 7declare void @llvm.amdgcn.exp.row.i32(i32, i32, i32, i32, i32, i32, i1, i32)8declare void @llvm.amdgcn.exp.row.f32(i32, i32, float, float, float, float, i1, i32)9declare i32 @llvm.amdgcn.workitem.id.x()10 11define amdgpu_kernel void @undef_i32() #0 {12; GFX11-LABEL: undef_i32:13; GFX11: ; %bb.0:14; GFX11-NEXT: s_mov_b32 m0, 015; GFX11-NEXT: exp pos0 off, off, off, off row_en16; GFX11-NEXT: exp pos1 off, off, off, off done row_en17; GFX11-NEXT: s_endpgm18;19; GFX12-LABEL: undef_i32:20; GFX12: ; %bb.0:21; GFX12-NEXT: s_mov_b32 m0, 022; GFX12-NEXT: export pos0 off, off, off, off row_en23; GFX12-NEXT: export pos1 off, off, off, off done row_en24; GFX12-NEXT: s_endpgm25 call void @llvm.amdgcn.exp.row.i32(i32 12, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i1 false, i32 0)26 call void @llvm.amdgcn.exp.row.i32(i32 13, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i1 true, i32 0)27 ret void28}29 30define amdgpu_kernel void @undef_f32() #0 {31; GFX11-LABEL: undef_f32:32; GFX11: ; %bb.0:33; GFX11-NEXT: s_mov_b32 m0, 034; GFX11-NEXT: exp pos0 off, off, off, off row_en35; GFX11-NEXT: exp pos1 off, off, off, off done row_en36; GFX11-NEXT: s_endpgm37;38; GFX12-LABEL: undef_f32:39; GFX12: ; %bb.0:40; GFX12-NEXT: s_mov_b32 m0, 041; GFX12-NEXT: export pos0 off, off, off, off row_en42; GFX12-NEXT: export pos1 off, off, off, off done row_en43; GFX12-NEXT: s_endpgm44 call void @llvm.amdgcn.exp.row.f32(i32 12, i32 0, float poison, float poison, float poison, float poison, i1 false, i32 0)45 call void @llvm.amdgcn.exp.row.f32(i32 13, i32 0, float poison, float poison, float poison, float poison, i1 true, i32 0)46 ret void47}48 49define amdgpu_kernel void @zero_i32() #0 {50; GFX11-LABEL: zero_i32:51; GFX11: ; %bb.0:52; GFX11-NEXT: v_mov_b32_e32 v0, 053; GFX11-NEXT: s_mov_b32 m0, 054; GFX11-NEXT: exp pos0 v0, v0, v0, off row_en55; GFX11-NEXT: exp pos1 v0, v0, v0, off done row_en56; GFX11-NEXT: s_endpgm57;58; GFX12-LABEL: zero_i32:59; GFX12: ; %bb.0:60; GFX12-NEXT: v_mov_b32_e32 v0, 061; GFX12-NEXT: s_mov_b32 m0, 062; GFX12-NEXT: export pos0 v0, v0, v0, off row_en63; GFX12-NEXT: export pos1 v0, v0, v0, off done row_en64; GFX12-NEXT: s_endpgm65 call void @llvm.amdgcn.exp.row.i32(i32 12, i32 7, i32 0, i32 0, i32 0, i32 poison, i1 false, i32 0)66 call void @llvm.amdgcn.exp.row.i32(i32 13, i32 7, i32 0, i32 0, i32 0, i32 poison, i1 true, i32 0)67 ret void68}69 70define amdgpu_kernel void @one_f32() #0 {71; GFX11-LABEL: one_f32:72; GFX11: ; %bb.0:73; GFX11-NEXT: v_mov_b32_e32 v0, 1.074; GFX11-NEXT: s_mov_b32 m0, 075; GFX11-NEXT: exp pos0 v0, v0, v0, off row_en76; GFX11-NEXT: exp pos1 v0, v0, v0, off done row_en77; GFX11-NEXT: s_endpgm78;79; GFX12-LABEL: one_f32:80; GFX12: ; %bb.0:81; GFX12-NEXT: v_mov_b32_e32 v0, 1.082; GFX12-NEXT: s_mov_b32 m0, 083; GFX12-NEXT: export pos0 v0, v0, v0, off row_en84; GFX12-NEXT: export pos1 v0, v0, v0, off done row_en85; GFX12-NEXT: s_endpgm86 call void @llvm.amdgcn.exp.row.f32(i32 12, i32 7, float 1.0, float 1.0, float 1.0, float poison, i1 false, i32 0)87 call void @llvm.amdgcn.exp.row.f32(i32 13, i32 7, float 1.0, float 1.0, float 1.0, float poison, i1 true, i32 0)88 ret void89}90 91define amdgpu_kernel void @id_i32() #0 {92; GFX11-LABEL: id_i32:93; GFX11: ; %bb.0:94; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v095; GFX11-NEXT: s_mov_b32 m0, 096; GFX11-NEXT: exp pos0 v0, off, off, off done row_en97; GFX11-NEXT: s_endpgm98;99; GFX12-LABEL: id_i32:100; GFX12: ; %bb.0:101; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0102; GFX12-NEXT: s_mov_b32 m0, 0103; GFX12-NEXT: export pos0 v0, off, off, off done row_en104; GFX12-NEXT: s_endpgm105 %id = call i32 @llvm.amdgcn.workitem.id.x()106 call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 %id, i32 poison, i32 poison, i32 poison, i1 true, i32 0)107 ret void108}109 110define amdgpu_kernel void @id_arg_i32(i32 %row) #0 {111; GFX11-LABEL: id_arg_i32:112; GFX11: ; %bb.0:113; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24114; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0115; GFX11-NEXT: s_waitcnt lgkmcnt(0)116; GFX11-NEXT: s_mov_b32 m0, s0117; GFX11-NEXT: exp pos0 v0, off, off, off done row_en118; GFX11-NEXT: s_endpgm119;120; GFX12-LABEL: id_arg_i32:121; GFX12: ; %bb.0:122; GFX12-NEXT: s_load_b32 s0, s[4:5], 0x24123; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0124; GFX12-NEXT: s_wait_kmcnt 0x0125; GFX12-NEXT: s_mov_b32 m0, s0126; GFX12-NEXT: export pos0 v0, off, off, off done row_en127; GFX12-NEXT: s_endpgm128 %id = call i32 @llvm.amdgcn.workitem.id.x()129 call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 %id, i32 poison, i32 poison, i32 poison, i1 true, i32 %row)130 ret void131}132 133; Divergent row number just causes a readfirstlane for now.134define amdgpu_kernel void @id_row_i32() #0 {135; GFX11-SDAG-LABEL: id_row_i32:136; GFX11-SDAG: ; %bb.0:137; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0138; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)139; GFX11-SDAG-NEXT: v_readfirstlane_b32 s0, v0140; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0x63141; GFX11-SDAG-NEXT: s_mov_b32 m0, s0142; GFX11-SDAG-NEXT: exp pos0 v0, off, off, off done row_en143; GFX11-SDAG-NEXT: s_endpgm144;145; GFX11-GISEL-LABEL: id_row_i32:146; GFX11-GISEL: ; %bb.0:147; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0148; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0x63149; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)150; GFX11-GISEL-NEXT: v_readfirstlane_b32 m0, v0151; GFX11-GISEL-NEXT: exp pos0 v1, off, off, off done row_en152; GFX11-GISEL-NEXT: s_endpgm153;154; GFX12-SDAG-LABEL: id_row_i32:155; GFX12-SDAG: ; %bb.0:156; GFX12-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0157; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)158; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v0159; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0x63160; GFX12-SDAG-NEXT: s_mov_b32 m0, s0161; GFX12-SDAG-NEXT: export pos0 v0, off, off, off done row_en162; GFX12-SDAG-NEXT: s_endpgm163;164; GFX12-GISEL-LABEL: id_row_i32:165; GFX12-GISEL: ; %bb.0:166; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0167; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, 0x63168; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)169; GFX12-GISEL-NEXT: v_readfirstlane_b32 m0, v0170; GFX12-GISEL-NEXT: export pos0 v1, off, off, off done row_en171; GFX12-GISEL-NEXT: s_endpgm172 %id = call i32 @llvm.amdgcn.workitem.id.x()173 call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 99, i32 poison, i32 poison, i32 poison, i1 true, i32 %id)174 ret void175}176