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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck %s --check-prefixes=GFX11,SDAG-GFX11,SDAG-GFX11-TRUE163; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck %s --check-prefixes=GFX11,SDAG-GFX11,SDAG-GFX11-FAKE164; FIXME: GlobalIsel doesn't support BF16 for now.5; xUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck %s --check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-TRUE166; xUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck %s --check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-FAKE167 8declare bfloat @llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> %a, <2 x bfloat> %b, bfloat %c)9 10define amdgpu_kernel void @test_llvm_amdgcn_fdot2_bf16_bf16(11; SDAG-GFX11-TRUE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16:12; SDAG-GFX11-TRUE16: ; %bb.0: ; %entry13; SDAG-GFX11-TRUE16-NEXT: s_load_b256 s[0:7], s[4:5], 0x2414; SDAG-GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 015; SDAG-GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)16; SDAG-GFX11-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x017; SDAG-GFX11-TRUE16-NEXT: s_load_b32 s3, s[4:5], 0x018; SDAG-GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[6:7]19; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)20; SDAG-GFX11-TRUE16-NEXT: v_dot2_bf16_bf16 v0.l, s2, s3, v0.l21; SDAG-GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]22; SDAG-GFX11-TRUE16-NEXT: s_endpgm23;24; SDAG-GFX11-FAKE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16:25; SDAG-GFX11-FAKE16: ; %bb.0: ; %entry26; SDAG-GFX11-FAKE16-NEXT: s_load_b256 s[0:7], s[4:5], 0x2427; SDAG-GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 028; SDAG-GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)29; SDAG-GFX11-FAKE16-NEXT: s_load_b32 s2, s[2:3], 0x030; SDAG-GFX11-FAKE16-NEXT: s_load_b32 s3, s[4:5], 0x031; SDAG-GFX11-FAKE16-NEXT: global_load_u16 v1, v0, s[6:7]32; SDAG-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)33; SDAG-GFX11-FAKE16-NEXT: v_dot2_bf16_bf16 v1, s2, s3, v134; SDAG-GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]35; SDAG-GFX11-FAKE16-NEXT: s_endpgm36 ptr addrspace(1) %r,37 ptr addrspace(1) %a,38 ptr addrspace(1) %b,39 ptr addrspace(1) %c) {40entry:41 %a.val = load <2 x bfloat>, ptr addrspace(1) %a42 %b.val = load <2 x bfloat>, ptr addrspace(1) %b43 %c.val = load bfloat, ptr addrspace(1) %c44 %r.val = call bfloat @llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> %a.val, <2 x bfloat> %b.val, bfloat %c.val)45 store bfloat %r.val, ptr addrspace(1) %r46 ret void47}48 49define amdgpu_kernel void @test_llvm_amdgcn_fdot2_bf16_bf16_dpp(50; SDAG-GFX11-TRUE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_dpp:51; SDAG-GFX11-TRUE16: ; %bb.0: ; %entry52; SDAG-GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2453; SDAG-GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)54; SDAG-GFX11-TRUE16-NEXT: scratch_load_b32 v1, off, s155; SDAG-GFX11-TRUE16-NEXT: scratch_load_b32 v2, off, s256; SDAG-GFX11-TRUE16-NEXT: scratch_load_d16_b16 v0, off, s357; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)58; SDAG-GFX11-TRUE16-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:159; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)60; SDAG-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)61; SDAG-GFX11-TRUE16-NEXT: v_dot2_bf16_bf16 v0.l, v1, v2, v0.l62; SDAG-GFX11-TRUE16-NEXT: scratch_store_b16 off, v0, s063; SDAG-GFX11-TRUE16-NEXT: s_endpgm64;65; SDAG-GFX11-FAKE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_dpp:66; SDAG-GFX11-FAKE16: ; %bb.0: ; %entry67; SDAG-GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2468; SDAG-GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)69; SDAG-GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s270; SDAG-GFX11-FAKE16-NEXT: scratch_load_u16 v1, off, s371; SDAG-GFX11-FAKE16-NEXT: scratch_load_b32 v2, off, s172; SDAG-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)73; SDAG-GFX11-FAKE16-NEXT: v_dot2_bf16_bf16_e64_dpp v0, v2, v0, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:174; SDAG-GFX11-FAKE16-NEXT: scratch_store_b16 off, v0, s075; SDAG-GFX11-FAKE16-NEXT: s_endpgm76 ptr addrspace(5) %r,77 ptr addrspace(5) %a,78 ptr addrspace(5) %b,79 ptr addrspace(5) %c) {80entry:81 %a.val = load <2 x bfloat>, ptr addrspace(5) %a82 %b.val = load <2 x bfloat>, ptr addrspace(5) %b83 %c.val = load bfloat, ptr addrspace(5) %c84 %a.val.i32 = bitcast <2 x bfloat> %a.val to i3285 %dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 %a.val.i32, i32 %a.val.i32, i32 1, i32 15, i32 15, i1 1)86 %a.val.dpp.v2bfloat = bitcast i32 %dpp to <2 x bfloat>87 %r.val = call bfloat @llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> %a.val.dpp.v2bfloat, <2 x bfloat> %b.val, bfloat %c.val)88 store bfloat %r.val, ptr addrspace(5) %r89 ret void90}91 92; Make sure we do not violate constant bus restriction with 3 scalar inputs and simingly inlinable literal.93 94define amdgpu_ps void @test_llvm_amdgcn_fdot2_bf16_bf16_sis(95; SDAG-GFX11-TRUE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_sis:96; SDAG-GFX11-TRUE16: ; %bb.0: ; %entry97; SDAG-GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, s198; SDAG-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)99; SDAG-GFX11-TRUE16-NEXT: v_dot2_bf16_bf16 v2.l, s0, 0x3f803f80, v2.l100; SDAG-GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v2, off101; SDAG-GFX11-TRUE16-NEXT: s_endpgm102;103; SDAG-GFX11-FAKE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_sis:104; SDAG-GFX11-FAKE16: ; %bb.0: ; %entry105; SDAG-GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, s1106; SDAG-GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)107; SDAG-GFX11-FAKE16-NEXT: v_dot2_bf16_bf16 v2, s0, 0x3f803f80, v2108; SDAG-GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v2, off109; SDAG-GFX11-FAKE16-NEXT: s_endpgm110 ptr addrspace(1) %r,111 <2 x bfloat> inreg %a,112 bfloat inreg %c) {113entry:114 %r.val = call bfloat @llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> %a, <2 x bfloat> <bfloat 1.0, bfloat 1.0>, bfloat %c)115 store bfloat %r.val, ptr addrspace(1) %r116 ret void117}118 119declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1)120;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:121; GFX11: {{.*}}122; SDAG-GFX11: {{.*}}123