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1; RUN: llc -mtriple=amdgcn -mcpu=tonga -denormal-fp-math-f32=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX8 %s2; RUN: llc -mtriple=amdgcn -mcpu=tonga -denormal-fp-math-f32=ieee < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX8 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math-f32=ieee < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s4 5declare half @llvm.amdgcn.fmad.ftz.f16(half %a, half %b, half %c)6 7; GCN-LABEL: {{^}}mad_f16:8; GCN: v_mac_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+$}}9define amdgpu_kernel void @mad_f16(10 ptr addrspace(1) %r,11 ptr addrspace(1) %a,12 ptr addrspace(1) %b,13 ptr addrspace(1) %c) {14 %a.val = load half, ptr addrspace(1) %a15 %b.val = load half, ptr addrspace(1) %b16 %c.val = load half, ptr addrspace(1) %c17 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half %a.val, half %b.val, half %c.val)18 store half %r.val, ptr addrspace(1) %r19 ret void20}21 22; GCN-LABEL: {{^}}mad_f16_imm_a:23; GCN: v_madmk_f16 {{v[0-9]+}}, {{v[0-9]+}}, 0x4800, {{v[0-9]+}}24define amdgpu_kernel void @mad_f16_imm_a(25 ptr addrspace(1) %r,26 ptr addrspace(1) %b,27 ptr addrspace(1) %c) {28 %b.val = load half, ptr addrspace(1) %b29 %c.val = load half, ptr addrspace(1) %c30 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half 8.0, half %b.val, half %c.val)31 store half %r.val, ptr addrspace(1) %r32 ret void33}34 35; GCN-LABEL: {{^}}mad_f16_imm_b:36; GCN: v_madmk_f16 {{v[0-9]+}}, {{v[0-9]+}}, 0x4800, {{v[0-9]+$}}37define amdgpu_kernel void @mad_f16_imm_b(38 ptr addrspace(1) %r,39 ptr addrspace(1) %a,40 ptr addrspace(1) %c) {41 %a.val = load half, ptr addrspace(1) %a42 %c.val = load half, ptr addrspace(1) %c43 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half %a.val, half 8.0, half %c.val)44 store half %r.val, ptr addrspace(1) %r45 ret void46}47 48; GCN-LABEL: {{^}}mad_f16_imm_c:49; GCN: v_madak_f16 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, 0x4800{{$}}50define amdgpu_kernel void @mad_f16_imm_c(51 ptr addrspace(1) %r,52 ptr addrspace(1) %a,53 ptr addrspace(1) %b) {54 %a.val = load half, ptr addrspace(1) %a55 %b.val = load half, ptr addrspace(1) %b56 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half %a.val, half %b.val, half 8.0)57 store half %r.val, ptr addrspace(1) %r58 ret void59}60 61; GCN-LABEL: {{^}}mad_f16_neg_b:62; GFX8: v_mad_f16 v{{[0-9]+}}, v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}63; GFX9: v_mad_legacy_f16 v{{[0-9]+}}, v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}64define amdgpu_kernel void @mad_f16_neg_b(65 ptr addrspace(1) %r,66 ptr addrspace(1) %a,67 ptr addrspace(1) %b,68 ptr addrspace(1) %c) {69 %a.val = load half, ptr addrspace(1) %a70 %b.val = load half, ptr addrspace(1) %b71 %c.val = load half, ptr addrspace(1) %c72 %neg.b = fsub half -0.0, %b.val73 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half %a.val, half %neg.b, half %c.val)74 store half %r.val, ptr addrspace(1) %r75 ret void76}77 78; GCN-LABEL: {{^}}mad_f16_abs_b:79; GFX8: v_mad_f16 v{{[0-9]+}}, v{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}}80; GFX9: v_mad_legacy_f16 v{{[0-9]+}}, v{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}}81define amdgpu_kernel void @mad_f16_abs_b(82 ptr addrspace(1) %r,83 ptr addrspace(1) %a,84 ptr addrspace(1) %b,85 ptr addrspace(1) %c) {86 %a.val = load half, ptr addrspace(1) %a87 %b.val = load half, ptr addrspace(1) %b88 %c.val = load half, ptr addrspace(1) %c89 %abs.b = call half @llvm.fabs.f16(half %b.val)90 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half %a.val, half %abs.b, half %c.val)91 store half %r.val, ptr addrspace(1) %r92 ret void93}94 95; GCN-LABEL: {{^}}mad_f16_neg_abs_b:96; GFX8: v_mad_f16 v{{[0-9]+}}, v{{[0-9]+}}, -|v{{[0-9]+}}|, v{{[0-9]+}}97; GFX9: v_mad_legacy_f16 v{{[0-9]+}}, v{{[0-9]+}}, -|v{{[0-9]+}}|, v{{[0-9]+}}98define amdgpu_kernel void @mad_f16_neg_abs_b(99 ptr addrspace(1) %r,100 ptr addrspace(1) %a,101 ptr addrspace(1) %b,102 ptr addrspace(1) %c) {103 %a.val = load half, ptr addrspace(1) %a104 %b.val = load half, ptr addrspace(1) %b105 %c.val = load half, ptr addrspace(1) %c106 %abs.b = call half @llvm.fabs.f16(half %b.val)107 %neg.abs.b = fsub half -0.0, %abs.b108 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half %a.val, half %neg.abs.b, half %c.val)109 store half %r.val, ptr addrspace(1) %r110 ret void111}112 113declare half @llvm.fabs.f16(half)114