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1; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s2 3; GCN-LABEL: {{^}}test_fmed3_f16:4; GCN: v_med3_f16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}5define amdgpu_kernel void @test_fmed3_f16(ptr addrspace(1) %out, i32 %src0.arg, i32 %src1.arg, i32 %src2.arg) #1 {6 %src0.f16 = trunc i32 %src0.arg to i167 %src0 = bitcast i16 %src0.f16 to half8 %src1.f16 = trunc i32 %src1.arg to i169 %src1 = bitcast i16 %src1.f16 to half10 %src2.f16 = trunc i32 %src2.arg to i1611 %src2 = bitcast i16 %src2.f16 to half12 %mad = call half @llvm.amdgcn.fmed3.f16(half %src0, half %src1, half %src2)13 store half %mad, ptr addrspace(1) %out14 ret void15}16 17; GCN-LABEL: {{^}}test_fmed3_srcmods_f16:18; GCN: v_med3_f16 v{{[0-9]+}}, -s{{[0-9]+}}, |v{{[0-9]+}}|, -|v{{[0-9]+}}|19define amdgpu_kernel void @test_fmed3_srcmods_f16(ptr addrspace(1) %out, i32 %src0.arg, i32 %src1.arg, i32 %src2.arg) #1 {20 %src0.f16 = trunc i32 %src0.arg to i1621 %src0 = bitcast i16 %src0.f16 to half22 %src1.f16 = trunc i32 %src1.arg to i1623 %src1 = bitcast i16 %src1.f16 to half24 %src2.f16 = trunc i32 %src2.arg to i1625 %src2 = bitcast i16 %src2.f16 to half26 %src0.fneg = fsub half -0.0, %src027 %src1.fabs = call half @llvm.fabs.f16(half %src1)28 %src2.fabs = call half @llvm.fabs.f16(half %src2)29 %src2.fneg.fabs = fsub half -0.0, %src2.fabs30 %mad = call half @llvm.amdgcn.fmed3.f16(half %src0.fneg, half %src1.fabs, half %src2.fneg.fabs)31 store half %mad, ptr addrspace(1) %out32 ret void33}34 35declare half @llvm.amdgcn.fmed3.f16(half, half, half) #036declare half @llvm.fabs.f16(half) #037 38attributes #0 = { nounwind readnone }39attributes #1 = { nounwind }40