107 lines · plain
1; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s2; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s3 4; GCN-LABEL: {{^}}test_fmed3:5; GCN: v_med3_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}6define amdgpu_kernel void @test_fmed3(ptr addrspace(1) %out, float %src0, float %src1, float %src2) #1 {7 %med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float %src2)8 store float %med3, ptr addrspace(1) %out9 ret void10}11 12; GCN-LABEL: {{^}}test_fmed3_srcmods:13; GCN: v_med3_f32 v{{[0-9]+}}, -s{{[0-9]+}}, |v{{[0-9]+}}|, -|v{{[0-9]+}}|14define amdgpu_kernel void @test_fmed3_srcmods(ptr addrspace(1) %out, float %src0, float %src1, float %src2) #1 {15 %src0.fneg = fsub float -0.0, %src016 %src1.fabs = call float @llvm.fabs.f32(float %src1)17 %src2.fabs = call float @llvm.fabs.f32(float %src2)18 %src2.fneg.fabs = fsub float -0.0, %src2.fabs19 %med3 = call float @llvm.amdgcn.fmed3.f32(float %src0.fneg, float %src1.fabs, float %src2.fneg.fabs)20 store float %med3, ptr addrspace(1) %out21 ret void22}23 24; GCN-LABEL: {{^}}test_fneg_fmed3:25; GCN: v_med3_f32 v{{[0-9]+}}, -s{{[0-9]+}}, -v{{[0-9]+}}, -v{{[0-9]+}}26define amdgpu_kernel void @test_fneg_fmed3(ptr addrspace(1) %out, float %src0, float %src1, float %src2) #1 {27 %med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float %src2)28 %neg.med3 = fsub float -0.0, %med329 store float %neg.med3, ptr addrspace(1) %out30 ret void31}32 33; GCN-LABEL: {{^}}test_fneg_fmed3_multi_use:34; GCN: v_med3_f32 [[MED3:v[0-9]+]], -s{{[0-9]+}}, -v{{[0-9]+}}, -v{{[0-9]+}}35; GCN: v_mul_f32_e32 v{{[0-9]+}}, -4.0, [[MED3]]36define amdgpu_kernel void @test_fneg_fmed3_multi_use(ptr addrspace(1) %out, float %src0, float %src1, float %src2) #1 {37 %med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float %src2)38 %neg.med3 = fsub float -0.0, %med339 %med3.user = fmul float %med3, 4.040 store volatile float %med3.user, ptr addrspace(1) %out41 store volatile float %neg.med3, ptr addrspace(1) %out42 ret void43}44 45; GCN-LABEL: {{^}}test_fabs_fmed3:46; GCN: v_med3_f32 [[MED3:v[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}47; GCN: v_and_b32_e32 v{{[0-9]+}}, 0x7fffffff, [[MED3]]48define amdgpu_kernel void @test_fabs_fmed3(ptr addrspace(1) %out, float %src0, float %src1, float %src2) #1 {49 %med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float %src2)50 %fabs.med3 = call float @llvm.fabs.f32(float %med3)51 store float %fabs.med3, ptr addrspace(1) %out52 ret void53}54 55; GCN-LABEL: {{^}}test_fneg_fmed3_rr_0:56; GCN: v_bfrev_b32_e32 [[NEG0:v[0-9]+]], 157; GCN: v_med3_f32 v{{[0-9]+}}, -s{{[0-9]+}}, -v{{[0-9]+}}, [[NEG0]]58define amdgpu_kernel void @test_fneg_fmed3_rr_0(ptr addrspace(1) %out, float %src0, float %src1) #1 {59 %med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float 0.0)60 %neg.med3 = fsub float -0.0, %med361 store float %neg.med3, ptr addrspace(1) %out62 ret void63}64 65; FIXME: Worse off from folding this66; GCN-LABEL: {{^}}test_fneg_fmed3_rr_0_foldable_user:67; GCN: v_bfrev_b32_e32 [[NEG0:v[0-9]+]], 168; GCN: v_med3_f32 [[MED3:v[0-9]+]], -s{{[0-9]+}}, -v{{[0-9]+}}, [[NEG0]]69; GCN: v_mul_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[MED3]]70define amdgpu_kernel void @test_fneg_fmed3_rr_0_foldable_user(ptr addrspace(1) %out, float %src0, float %src1, float %mul.arg) #1 {71 %med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float 0.0)72 %neg.med3 = fsub float -0.0, %med373 %mul = fmul float %neg.med3, %mul.arg74 store float %mul, ptr addrspace(1) %out75 ret void76}77 78; GCN-LABEL: {{^}}test_fneg_fmed3_r_inv2pi_0:79; GCN-DAG: v_bfrev_b32_e32 [[NEG0:v[0-9]+]], 180; GCN-DAG: v_mov_b32_e32 [[NEG_INV:v[0-9]+]], 0xbe22f98381; GCN: v_med3_f32 v{{[0-9]+}}, -s{{[0-9]+}}, [[NEG_INV]], [[NEG0]]82define amdgpu_kernel void @test_fneg_fmed3_r_inv2pi_0(ptr addrspace(1) %out, float %src0) #1 {83 %med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float 0x3FC45F3060000000, float 0.0)84 %neg.med3 = fsub float -0.0, %med385 store float %neg.med3, ptr addrspace(1) %out86 ret void87}88 89; GCN-LABEL: {{^}}test_fneg_fmed3_r_inv2pi_0_foldable_user:90; GCN-DAG: v_bfrev_b32_e32 [[NEG0:v[0-9]+]], 191; GCN-DAG: v_mov_b32_e32 [[NEG_INV:v[0-9]+]], 0xbe22f98392; GCN: v_med3_f32 [[MED3:v[0-9]+]], -s{{[0-9]+}}, [[NEG_INV]], [[NEG0]]93; GCN: v_mul_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[MED3]]94define amdgpu_kernel void @test_fneg_fmed3_r_inv2pi_0_foldable_user(ptr addrspace(1) %out, float %src0, float %mul.arg) #1 {95 %med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float 0x3FC45F3060000000, float 0.0)96 %neg.med3 = fsub float -0.0, %med397 %mul = fmul float %neg.med3, %mul.arg98 store float %mul, ptr addrspace(1) %out99 ret void100}101 102declare float @llvm.amdgcn.fmed3.f32(float, float, float) #0103declare float @llvm.fabs.f32(float) #0104 105attributes #0 = { nounwind readnone }106attributes #1 = { nounwind }107