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1; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s2 3declare i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a)4 5; GCN-LABEL: {{^}}frexp_exp_f166; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]7; VI: v_frexp_exp_i16_f16_e32 v[[R_I16:[0-9]+]], v[[A_F16]]8; GCN: buffer_store_short v[[R_I16]]9define amdgpu_kernel void @frexp_exp_f16(10 ptr addrspace(1) %r,11 ptr addrspace(1) %a) {12entry:13 %a.val = load half, ptr addrspace(1) %a14 %r.val = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a.val)15 store i16 %r.val, ptr addrspace(1) %r16 ret void17}18 19; GCN-LABEL: {{^}}frexp_exp_f16_sext20; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]21; VI: v_frexp_exp_i16_f16_e32 v[[R_I16:[0-9]+]], v[[A_F16]]22; VI: v_bfe_i32 v[[R_I32:[0-9]+]], v[[R_I16]], 0, 16{{$}}23; GCN: buffer_store_dword v[[R_I32]]24define amdgpu_kernel void @frexp_exp_f16_sext(25 ptr addrspace(1) %r,26 ptr addrspace(1) %a) {27entry:28 %a.val = load half, ptr addrspace(1) %a29 %r.val = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a.val)30 %r.val.sext = sext i16 %r.val to i3231 store i32 %r.val.sext, ptr addrspace(1) %r32 ret void33}34 35; GCN-LABEL: {{^}}frexp_exp_f16_zext36; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]37; VI: v_frexp_exp_i16_f16_e32 v[[R_I16:[0-9]+]], v[[A_F16]]38; GCN: buffer_store_dword v[[R_I16]]39define amdgpu_kernel void @frexp_exp_f16_zext(40 ptr addrspace(1) %r,41 ptr addrspace(1) %a) {42entry:43 %a.val = load half, ptr addrspace(1) %a44 %r.val = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a.val)45 %r.val.zext = zext i16 %r.val to i3246 store i32 %r.val.zext, ptr addrspace(1) %r47 ret void48}49