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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX950,GFX950-SDAG %s3; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX950,GFX950-GISEL %s4 5; RUN: not --crash llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 -filetype=null < %s 2>&1 | FileCheck -check-prefix=ERR-SDAG %s6; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 -filetype=null < %s 2>&1 | FileCheck -check-prefix=ERR-GISEL %s7 8; ERR-SDAG: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.global.load.lds9 10; ERR-GISEL: LLVM ERROR: cannot select: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.global.load.lds),11 12 13declare void @llvm.amdgcn.global.load.lds(ptr addrspace(1) nocapture %gptr, ptr addrspace(3) nocapture %lptr, i32 %size, i32 %offset, i32 %aux)14 15;---------------------------------------------------------------------y16; dwordx317;---------------------------------------------------------------------18 19define amdgpu_ps void @global_load_lds_dwordx3_vaddr(ptr addrspace(1) nocapture %gptr, ptr addrspace(3) nocapture %lptr) {20; GFX950-LABEL: global_load_lds_dwordx3_vaddr:21; GFX950: ; %bb.0:22; GFX950-NEXT: v_readfirstlane_b32 s0, v223; GFX950-NEXT: s_mov_b32 m0, s024; GFX950-NEXT: s_nop 025; GFX950-NEXT: global_load_lds_dwordx3 v[0:1], off offset:16 sc026; GFX950-NEXT: s_endpgm27 call void @llvm.amdgcn.global.load.lds(ptr addrspace(1) %gptr, ptr addrspace(3) %lptr, i32 12, i32 16, i32 1)28 ret void29}30 31define amdgpu_ps void @global_load_lds_dwordx3_saddr(ptr addrspace(1) nocapture inreg %gptr, ptr addrspace(3) nocapture %lptr) {32; GFX950-SDAG-LABEL: global_load_lds_dwordx3_saddr:33; GFX950-SDAG: ; %bb.0:34; GFX950-SDAG-NEXT: v_readfirstlane_b32 s2, v035; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 036; GFX950-SDAG-NEXT: s_mov_b32 m0, s237; GFX950-SDAG-NEXT: s_nop 038; GFX950-SDAG-NEXT: global_load_lds_dwordx3 v1, s[0:1] offset:32 nt39; GFX950-SDAG-NEXT: s_endpgm40;41; GFX950-GISEL-LABEL: global_load_lds_dwordx3_saddr:42; GFX950-GISEL: ; %bb.0:43; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v044; GFX950-GISEL-NEXT: v_mov_b32_e32 v0, 045; GFX950-GISEL-NEXT: s_mov_b32 m0, s246; GFX950-GISEL-NEXT: s_nop 047; GFX950-GISEL-NEXT: global_load_lds_dwordx3 v0, s[0:1] offset:32 nt48; GFX950-GISEL-NEXT: s_endpgm49 call void @llvm.amdgcn.global.load.lds(ptr addrspace(1) %gptr, ptr addrspace(3) %lptr, i32 12, i32 32, i32 2)50 ret void51}52 53define amdgpu_ps void @global_load_lds_dwordx3_saddr_and_vaddr(ptr addrspace(1) nocapture inreg %gptr, ptr addrspace(3) nocapture %lptr, i32 %voffset) {54; GFX950-LABEL: global_load_lds_dwordx3_saddr_and_vaddr:55; GFX950: ; %bb.0:56; GFX950-NEXT: v_readfirstlane_b32 s2, v057; GFX950-NEXT: s_mov_b32 m0, s258; GFX950-NEXT: s_nop 059; GFX950-NEXT: global_load_lds_dwordx3 v1, s[0:1] offset:48 sc160; GFX950-NEXT: s_endpgm61 %voffset.64 = zext i32 %voffset to i6462 %gep = getelementptr i8, ptr addrspace(1) %gptr, i64 %voffset.6463 call void @llvm.amdgcn.global.load.lds(ptr addrspace(1) %gep, ptr addrspace(3) %lptr, i32 12, i32 48, i32 16)64 ret void65}66 67;---------------------------------------------------------------------68; dwordx469;---------------------------------------------------------------------70 71define amdgpu_ps void @global_load_lds_dwordx4_vaddr(ptr addrspace(1) nocapture %gptr, ptr addrspace(3) nocapture %lptr) {72; GFX950-LABEL: global_load_lds_dwordx4_vaddr:73; GFX950: ; %bb.0:74; GFX950-NEXT: v_readfirstlane_b32 s0, v275; GFX950-NEXT: s_mov_b32 m0, s076; GFX950-NEXT: s_nop 077; GFX950-NEXT: global_load_lds_dwordx4 v[0:1], off offset:16 sc078; GFX950-NEXT: s_endpgm79 call void @llvm.amdgcn.global.load.lds(ptr addrspace(1) %gptr, ptr addrspace(3) %lptr, i32 16, i32 16, i32 1)80 ret void81}82 83define amdgpu_ps void @global_load_lds_dwordx4_saddr(ptr addrspace(1) nocapture inreg %gptr, ptr addrspace(3) nocapture %lptr) {84; GFX950-SDAG-LABEL: global_load_lds_dwordx4_saddr:85; GFX950-SDAG: ; %bb.0:86; GFX950-SDAG-NEXT: v_readfirstlane_b32 s2, v087; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 088; GFX950-SDAG-NEXT: s_mov_b32 m0, s289; GFX950-SDAG-NEXT: s_nop 090; GFX950-SDAG-NEXT: global_load_lds_dwordx4 v1, s[0:1] offset:32 nt91; GFX950-SDAG-NEXT: s_endpgm92;93; GFX950-GISEL-LABEL: global_load_lds_dwordx4_saddr:94; GFX950-GISEL: ; %bb.0:95; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v096; GFX950-GISEL-NEXT: v_mov_b32_e32 v0, 097; GFX950-GISEL-NEXT: s_mov_b32 m0, s298; GFX950-GISEL-NEXT: s_nop 099; GFX950-GISEL-NEXT: global_load_lds_dwordx4 v0, s[0:1] offset:32 nt100; GFX950-GISEL-NEXT: s_endpgm101 call void @llvm.amdgcn.global.load.lds(ptr addrspace(1) %gptr, ptr addrspace(3) %lptr, i32 16, i32 32, i32 2)102 ret void103}104 105define amdgpu_ps void @global_load_lds_dwordx4_saddr_and_vaddr(ptr addrspace(1) nocapture inreg %gptr, ptr addrspace(3) nocapture %lptr, i32 %voffset) {106; GFX950-LABEL: global_load_lds_dwordx4_saddr_and_vaddr:107; GFX950: ; %bb.0:108; GFX950-NEXT: v_readfirstlane_b32 s2, v0109; GFX950-NEXT: s_mov_b32 m0, s2110; GFX950-NEXT: s_nop 0111; GFX950-NEXT: global_load_lds_dwordx4 v1, s[0:1] offset:48 sc1112; GFX950-NEXT: s_endpgm113 %voffset.64 = zext i32 %voffset to i64114 %gep = getelementptr i8, ptr addrspace(1) %gptr, i64 %voffset.64115 call void @llvm.amdgcn.global.load.lds(ptr addrspace(1) %gep, ptr addrspace(3) %lptr, i32 16, i32 48, i32 16)116 ret void117}118